Cc: Alex Dai <yu.dai@intel.com>
Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
 #define   START_DMA                      (1<<0)
 #define DMA_GUC_WOPCM_OFFSET           0xc340
 #define   GUC_WOPCM_OFFSET_VALUE         0x80000       /* 512KB */
+#define GUC_MAX_IDLE_COUNT             0xC3E4
 
 #define GUC_WOPCM_SIZE                 0xc050
 #define   GUC_WOPCM_SIZE_VALUE           (0x80 << 12)  /* 512KB */
 
        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
        for_each_ring(ring, dev_priv, unused)
                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+       if (HAS_GUC_UCODE(dev))
+               I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
+
        I915_WRITE(GEN6_RC_SLEEP, 0);
        I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */