} ce_payload = {};
 
        if (ring->adev->virt.chained_ib_support) {
-               ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 +
-                                                 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
+               ce_payload_addr = AMDGPU_CSA_VADDR +
+                       offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
                cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
        } else {
-               ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 +
-                                                 offsetof(struct vi_gfx_meta_data, ce_payload);
+               ce_payload_addr = AMDGPU_CSA_VADDR +
+                       offsetof(struct vi_gfx_meta_data, ce_payload);
                cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
        }
 
                struct vi_de_ib_state_chained_ib chained;
        } de_payload = {};
 
-       csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
+       csa_addr = AMDGPU_CSA_VADDR;
        gds_addr = csa_addr + 4096;
        if (ring->adev->virt.chained_ib_support) {
                de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
 
        int cnt;
 
        cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
-       csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
+       csa_addr = AMDGPU_CSA_VADDR;
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
        uint64_t csa_addr, gds_addr;
        int cnt;
 
-       csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
+       csa_addr = AMDGPU_CSA_VADDR;
        gds_addr = csa_addr + 4096;
        de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
        de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);