drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()

Hoover the remaining open coded PCH modeset sequence bits
out from ilk_crtc_disable(). Somewhat annoyingly the
enable vs. disable is a bit asymmetric so we need two
functions for the disable case.

Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211015071625.593-8-ville.syrjala@linux.intel.com
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9bac7418fe3fc33b124960e0b0f2d4221536d0a6..79a7552af7b5e5eb02825c29b43b651dd1778b5d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2287,33 +2287,12 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
        ilk_pfit_disable(old_crtc_state);
 
        if (old_crtc_state->has_pch_encoder)
-               ilk_fdi_disable(crtc);
+               ilk_pch_disable(state, crtc);
 
        intel_encoders_post_disable(state, crtc);
 
-       if (old_crtc_state->has_pch_encoder) {
-               ilk_disable_pch_transcoder(crtc);
-
-               if (HAS_PCH_CPT(dev_priv)) {
-                       i915_reg_t reg;
-                       u32 temp;
-
-                       /* disable TRANS_DP_CTL */
-                       reg = TRANS_DP_CTL(pipe);
-                       temp = intel_de_read(dev_priv, reg);
-                       temp &= ~(TRANS_DP_OUTPUT_ENABLE |
-                                 TRANS_DP_PORT_SEL_MASK);
-                       temp |= TRANS_DP_PORT_SEL_NONE;
-                       intel_de_write(dev_priv, reg, temp);
-
-                       /* disable DPLL_SEL */
-                       temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
-                       temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
-                       intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
-               }
-
-               ilk_fdi_pll_disable(crtc);
-       }
+       if (old_crtc_state->has_pch_encoder)
+               ilk_pch_post_disable(state, crtc);
 
        intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
        intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 98b7b2c050cf82a2355fe61c5e1e05f0a1810006..a4939ac65dfb8406ab69207d1abb37d345292b31 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -179,7 +179,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
                        pipe_name(pipe));
 }
 
-void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
+static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
@@ -299,6 +299,41 @@ void ilk_pch_enable(struct intel_atomic_state *state,
        ilk_enable_pch_transcoder(crtc_state);
 }
 
+void ilk_pch_disable(struct intel_atomic_state *state,
+                    struct intel_crtc *crtc)
+{
+       ilk_fdi_disable(crtc);
+}
+
+void ilk_pch_post_disable(struct intel_atomic_state *state,
+                         struct intel_crtc *crtc)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum pipe pipe = crtc->pipe;
+
+       ilk_disable_pch_transcoder(crtc);
+
+       if (HAS_PCH_CPT(dev_priv)) {
+               i915_reg_t reg;
+               u32 temp;
+
+               /* disable TRANS_DP_CTL */
+               reg = TRANS_DP_CTL(pipe);
+               temp = intel_de_read(dev_priv, reg);
+               temp &= ~(TRANS_DP_OUTPUT_ENABLE |
+                         TRANS_DP_PORT_SEL_MASK);
+               temp |= TRANS_DP_PORT_SEL_NONE;
+               intel_de_write(dev_priv, reg, temp);
+
+               /* disable DPLL_SEL */
+               temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+               temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
+               intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+       }
+
+       ilk_fdi_pll_disable(crtc);
+}
+
 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 6e834fbebd64ad9c8f58fa3363cdf2904fdc4f79..a983f4d5a3b6cbeafcea07e66d2979d95b605c2d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -11,9 +11,12 @@ struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
 
-void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
 void ilk_pch_enable(struct intel_atomic_state *state,
                    struct intel_crtc *crtc);
+void ilk_pch_disable(struct intel_atomic_state *state,
+                    struct intel_crtc *crtc);
+void ilk_pch_post_disable(struct intel_atomic_state *state,
+                         struct intel_crtc *crtc);
 void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
 
 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);