drm/amd/display: Add margin for max vblank time for SubVP + DRR

[Description]
- Incorporate FW delays as port of max VTOTAL calculated for
  SubVP + DRR cases (since it is part of the microschedule).
- Also add margin for the max VTOTAL possible for SubVP + DRR cases.
- Due to rounding errors in FW (integer arithmetic), the microschedule
  calculation can get pushed to the next frame (incorrectly) in cases
  where we use the max VTOTAL possible to complete the MCLK switch.
- When the rounding error occurs, we are only off by 1-2 lines,
  use 40us margin which is working consistently.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d691218095243997b83b91c439a12557e54109e2..1ec1b441d5cba7566b047df908c41b3494aa3782 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -261,6 +261,7 @@ struct dc_caps {
        uint32_t cache_line_size;
        uint32_t cache_num_ways;
        uint16_t subvp_fw_processing_delay_us;
+       uint8_t subvp_drr_max_vblank_margin_us;
        uint16_t subvp_prefetch_end_to_mall_start_us;
        uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
        uint16_t subvp_pstate_allow_width_us;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 4cb912bf400b1e1ad7ec0e4df3bca125a6c1c633..097556f7b32cff2b518dc770f82f82b587ce738b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -477,12 +477,20 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
                        (((uint64_t)main_timing->pix_clk_100hz * 100)));
        drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
                        (((uint64_t)drr_timing->pix_clk_100hz * 100)));
-       max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us;
-       max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us;
+       max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
+                       dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
+       max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
        max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
        max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
                        (((uint64_t)drr_timing->h_total * 1000000)));
 
+       /* When calculating the max vtotal supported for SubVP + DRR cases, add
+        * margin due to possible rounding errors (being off by 1 line in the
+        * FW calculation can incorrectly push the P-State switch to wait 1 frame
+        * longer).
+        */
+       max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
+
        pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
        pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 4bd861427b3ca136eb5bf0cc7d723441ab9debce..77e40ee488bd628be2bc17b9ed7bd62f2faa9c8c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2117,6 +2117,7 @@ static bool dcn32_resource_construct(
        dc->caps.cache_num_ways = 16;
        dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
        dc->caps.subvp_fw_processing_delay_us = 15;
+       dc->caps.subvp_drr_max_vblank_margin_us = 40;
        dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
        dc->caps.subvp_swath_height_margin_lines = 16;
        dc->caps.subvp_pstate_allow_width_us = 20;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 6292ac515d1a448b8b492cd3fe6bc6081cfcb3b3..e5861225f1df9afef54692370797cff04a19448a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1704,6 +1704,7 @@ static bool dcn321_resource_construct(
        dc->caps.cache_num_ways = 16;
        dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32
        dc->caps.subvp_fw_processing_delay_us = 15;
+       dc->caps.subvp_drr_max_vblank_margin_us = 40;
        dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
        dc->caps.subvp_swath_height_margin_lines = 16;
        dc->caps.subvp_pstate_allow_width_us = 20;