drm/amd/display: Enable runtime register offset init for DCN32 DMUB

[Why&How]
DMUB subsystem was continuing to use compile time offset calculation for
register access. Switch this to runtime calculation to stay consistent
with rest of DC code.

To enable this, an additional interface init_reg_offsets() are added to
DMUB's hw_funcs struct. Asics with runtime register offset calculation
enabled shall populate this hook with a fn pointer that will invoke the
necessary macros to calculate the offset.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f2b4f1720abdeb7bb841634bdf332951925ca374..3ce63e98e9ce7ca5474afe7d4d2ae3025c1613a6 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1069,6 +1069,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
        const struct firmware *dmub_fw = adev->dm.dmub_fw;
        struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
        struct abm *abm = adev->dm.dc->res_pool->abm;
+       struct dc_context *ctx = adev->dm.dc->ctx;
        struct dmub_srv_hw_params hw_params;
        enum dmub_status status;
        const unsigned char *fw_inst_const, *fw_bss_data;
@@ -1090,6 +1091,10 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
                return -EINVAL;
        }
 
+       /* initialize register offsets for ASICs with runtime initialization available */
+       if (dmub_srv->hw_funcs.init_reg_offsets)
+               dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
+
        status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
        if (status != DMUB_STATUS_OK) {
                DRM_ERROR("Error checking HW support for DMUB: %d\n", status);

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 2d995c87fbb986aef9e0366773452b9a07d92f0e..43676c1c81d9fe40cb9abfdcbc1426646b21f360 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -65,6 +65,7 @@
  */
 
 #include "inc/dmub_cmd.h"
+#include "dc/dc_types.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -399,6 +400,7 @@ struct dmub_srv_hw_funcs {
        void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);
 
        bool (*should_detect)(struct dmub_srv *dmub);
+       void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);
 };
 
 /**
@@ -438,7 +440,7 @@ struct dmub_srv {
        /* private: internal use only */
        const struct dmub_srv_common_regs *regs;
        const struct dmub_srv_dcn31_regs *regs_dcn31;
-       const struct dmub_srv_dcn32_regs *regs_dcn32;
+       struct dmub_srv_dcn32_regs *regs_dcn32;
 
        struct dmub_srv_base_funcs funcs;
        struct dmub_srv_hw_funcs hw_funcs;

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index bf5994e292d9467f533ccf75eab21e0bb45b906e..8f427047ac407b681c81abfeacd1088709a0a5e7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -26,33 +26,39 @@
 #include "../dmub_srv.h"
 #include "dmub_reg.h"
 #include "dmub_dcn32.h"
+#include "dc/dc_types.h"
 
 #include "dcn/dcn_3_2_0_offset.h"
 #include "dcn/dcn_3_2_0_sh_mask.h"
 
 #define DCN_BASE__INST0_SEG2                       0x000034C0
 
-#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 #define CTX dmub
 #define REGS dmub->regs_dcn32
-#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
-
-const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
-#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
-       {
-               DMUB_DCN32_REGS()
-               DMCUB_INTERNAL_REGS()
-       },
+#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
+
+void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub,  struct dc_context *ctx)
+{
+       struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32;
+
+#define REG_STRUCT regs
+
+#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
+       DMUB_DCN32_REGS()
+       DMCUB_INTERNAL_REGS()
 #undef DMUB_SR
 
-#define DMUB_SF(reg, field) FD_MASK(reg, field),
-               { DMUB_DCN32_FIELDS() },
+#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
+       DMUB_DCN32_FIELDS()
 #undef DMUB_SF
 
-#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
-               { DMUB_DCN32_FIELDS() },
+#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
+       DMUB_DCN32_FIELDS()
 #undef DMUB_SF
-};
+
+#undef REG_STRUCT
+}
 
 static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
                uint64_t *fb_base,

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
index d58a1e4b9f1c12340e3afe8235bfed9a509ce914..38e47065e00e444f3afe2c3b547718a004d5f327 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
@@ -178,13 +178,11 @@ struct dmub_srv_dcn32_reg_mask {
 };
 
 struct dmub_srv_dcn32_regs {
-       const struct dmub_srv_dcn32_reg_offset offset;
-       const struct dmub_srv_dcn32_reg_mask mask;
-       const struct dmub_srv_dcn32_reg_shift shift;
+       struct dmub_srv_dcn32_reg_offset offset;
+       struct dmub_srv_dcn32_reg_mask mask;
+       struct dmub_srv_dcn32_reg_shift shift;
 };
 
-extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
-
 void dmub_dcn32_reset(struct dmub_srv *dmub);
 
 void dmub_dcn32_reset_release(struct dmub_srv *dmub);
@@ -256,4 +254,6 @@ void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_re
 void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);
 uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);
 
+void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
+
 #endif /* _DMUB_DCN32_H_ */

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 93624ffe4eb82447939c9e813944cb14697f294b..9780c157196c36daaebb1addc4a3e905c590b6b1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -78,6 +78,8 @@
 
 #define DMUB_REGION5_BASE (0xA0000000)
 
+static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
+
 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
 {
        return (val + factor - 1) / factor * factor;
@@ -304,6 +306,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
                funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
                funcs->get_current_time = dmub_dcn32_get_current_time;
                funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
+               funcs->init_reg_offsets = dmub_srv_dcn32_regs_init;
 
                break;