* While somewhat nonintuitive, this is an efficient way to get the data.
*/
- unsigned i = 0;
+ unsigned int i = 0;
do {
status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
if (status == DBUS_STATUS_BUSY)
static void dbus_write(struct target *target, uint16_t address, uint64_t value)
{
dbus_status_t status = DBUS_STATUS_BUSY;
- unsigned i = 0;
+ unsigned int i = 0;
while (status == DBUS_STATUS_BUSY && i++ < 256) {
status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
if (status == DBUS_STATUS_BUSY)
}
static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
- unsigned first, unsigned num)
+ unsigned int first, unsigned int num)
{
return buf_get_u32(scans->in + scans->scan_size * index, first, num);
}
static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
- unsigned first, unsigned num)
+ unsigned int first, unsigned int num)
{
return buf_get_u64(scans->in + scans->scan_size * index, first, num);
}
};
do {
- unsigned i = 0;
+ unsigned int i = 0;
do {
status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
if (status == DBUS_STATUS_BUSY) {
int result = update_mstatus_actual(target);
if (result != ERROR_OK)
return result;
- unsigned i = 0;
+ unsigned int i = 0;
if ((info->mstatus_actual & MSTATUS_FS) == 0) {
info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
cache_set_load(target, i++, S0, SLOT1);
int result = update_mstatus_actual(target);
if (result != ERROR_OK)
return result;
- unsigned i = 0;
+ unsigned int i = 0;
if ((info->mstatus_actual & MSTATUS_FS) == 0) {
info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
cache_set_load(target, i++, S0, SLOT1);
/* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */
cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
cache_set_jump(target, 5);
- for (unsigned i = 6; i < info->dramsize; i++)
+ for (unsigned int i = 6; i < info->dramsize; i++)
cache_set32(target, i, i * 0x01020304);
cache_write(target, 0, false);
LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
if (read_remote_csr(target, &r->misa, CSR_MISA) != ERROR_OK) {
- const unsigned old_csr_misa = 0xf10;
+ const unsigned int old_csr_misa = 0xf10;
LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
old_csr_misa);
if (read_remote_csr(target, &r->misa, old_csr_misa) != ERROR_OK) {
unsigned int dbus_busy = 0;
unsigned int interrupt_set = 0;
- unsigned result = 0;
+ unsigned int result = 0;
uint64_t value = 0;
reg_cache_set(target, 0, 0);
/* The first scan result is the result from something old we don't care
cache_write(target, CACHE_NO_READ, false);
riscv011_info_t *info = get_info(target);
- const unsigned max_batch_size = 256;
+ const unsigned int max_batch_size = 256;
scans_t *scans = scans_new(target, max_batch_size);
if (!scans)
return ERROR_FAIL;
if (setup_write_memory(target, size) != ERROR_OK)
return ERROR_FAIL;
- const unsigned max_batch_size = 256;
+ const unsigned int max_batch_size = 256;
scans_t *scans = scans_new(target, max_batch_size);
if (!scans)
return ERROR_FAIL;
static int riscv013_resume_prep(struct target *target);
static bool riscv013_is_halted(struct target *target);
static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
-static int riscv013_write_debug_buffer(struct target *target, unsigned index,
+static int riscv013_write_debug_buffer(struct target *target, unsigned int index,
riscv_insn_t d);
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned
index);
static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf);
static int register_read(struct target *target, uint64_t *value, uint32_t number);
static int register_read_direct(struct target *target, uint64_t *value, uint32_t number);
-static int register_write_direct(struct target *target, unsigned number,
+static int register_write_direct(struct target *target, unsigned int number,
uint64_t value);
static int read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
typedef struct {
/* The indexed used to address this hart in its DM. */
- unsigned index;
+ unsigned int index;
/* Number of address bits in the dbus register. */
- unsigned abits;
+ unsigned int abits;
/* Number of abstract command data registers. */
- unsigned datacount;
+ unsigned int datacount;
/* Number of words in the Program Buffer. */
- unsigned progbufsize;
+ unsigned int progbufsize;
/* We cache the read-only bits of sbcs here. */
uint32_t sbcs;
int16_t dataaddr;
/* The width of the hartsel field. */
- unsigned hartsellen;
+ unsigned int hartsellen;
/* DM that provides access to this target. */
dm013_info_t *dm;
return initial;
}
-static void decode_dmi(char *text, unsigned address, unsigned data)
+static void decode_dmi(char *text, unsigned int address, unsigned int data)
{
static const struct {
- unsigned address;
+ unsigned int address;
uint64_t mask;
const char *name;
} description[] = {
};
text[0] = 0;
- for (unsigned i = 0; i < ARRAY_SIZE(description); i++) {
+ for (unsigned int i = 0; i < ARRAY_SIZE(description); i++) {
if (description[i].address == address) {
uint64_t mask = description[i].mask;
- unsigned value = get_field(data, mask);
+ unsigned int value = get_field(data, mask);
if (value) {
if (i > 0)
*(text++) = ' ';
{
riscv013_info_t *info = get_info(target);
RISCV_INFO(r);
- unsigned num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH;
+ unsigned int num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH;
size_t num_bytes = (num_bits + 7) / 8;
uint8_t in[num_bytes];
uint8_t out[num_bytes];
}
static int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus,
- bool authenticated, unsigned timeout_sec)
+ bool authenticated, unsigned int timeout_sec)
{
int result = dmi_op_timeout(target, dmstatus, NULL, DMI_OP_READ,
DM_DMSTATUS, 0, timeout_sec, false, true);
info->ac_busy_delay);
}
-static uint32_t __attribute__((unused)) abstract_register_size(unsigned width)
+static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width)
{
switch (width) {
case 32:
return ERROR_OK;
}
-static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
- unsigned size_bits)
+static riscv_reg_t read_abstract_arg(struct target *target, unsigned int index,
+ unsigned int size_bits)
{
riscv_reg_t value = 0;
uint32_t v;
- unsigned offset = index * size_bits / 32;
+ unsigned int offset = index * size_bits / 32;
switch (size_bits) {
default:
LOG_ERROR("Unsupported size: %d bits", size_bits);
return value;
}
-static int write_abstract_arg(struct target *target, unsigned index,
- riscv_reg_t value, unsigned size_bits)
+static int write_abstract_arg(struct target *target, unsigned int index,
+ riscv_reg_t value, unsigned int size_bits)
{
- unsigned offset = index * size_bits / 32;
+ unsigned int offset = index * size_bits / 32;
switch (size_bits) {
default:
LOG_ERROR("Unsupported size: %d bits", size_bits);
* @par size in bits
*/
static uint32_t access_register_command(struct target *target, uint32_t number,
- unsigned size, uint32_t flags)
+ unsigned int size, uint32_t flags)
{
uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
switch (size) {
}
static int register_read_abstract(struct target *target, uint64_t *value,
- uint32_t number, unsigned size)
+ uint32_t number, unsigned int size)
{
RISCV013_INFO(info);
}
static int register_write_abstract(struct target *target, uint32_t number,
- uint64_t value, unsigned size)
+ uint64_t value, unsigned int size)
{
RISCV013_INFO(info);
* Sets the AAMSIZE field of a memory access abstract command based on
* the width (bits).
*/
-static uint32_t abstract_memory_size(unsigned width)
+static uint32_t abstract_memory_size(unsigned int width)
{
switch (width) {
case 8:
* Creates a memory access abstract command.
*/
static uint32_t access_memory_command(struct target *target, bool virtual,
- unsigned width, bool postincrement, bool write)
+ unsigned int width, bool postincrement, bool write)
{
uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
static int scratch_reserve(struct target *target,
scratch_mem_t *scratch,
struct riscv_program *program,
- unsigned size_bytes)
+ unsigned int size_bytes)
{
riscv_addr_t alignment = 1;
while (alignment < size_bytes)
return ERROR_FAIL;
/* Allow for ebreak at the end of the program. */
- unsigned program_size = (program->instruction_count + 1) * 4;
+ unsigned int program_size = (program->instruction_count + 1) * 4;
scratch->hart_address = (info->progbuf_address + program_size + alignment - 1) &
~(alignment - 1);
if ((info->progbuf_writable == YNM_YES) &&
}
/** Return register size in bits. */
-static unsigned register_size(struct target *target, unsigned number)
+static unsigned int register_size(struct target *target, unsigned int number)
{
/* If reg_cache hasn't been initialized yet, make a guess. We need this for
* when this function is called during examine(). */
return riscv_xlen(target);
}
-static bool has_sufficient_progbuf(struct target *target, unsigned size)
+static bool has_sufficient_progbuf(struct target *target, unsigned int size)
{
RISCV013_INFO(info);
RISCV_INFO(r);
* Immediately write the new value to the requested register. This mechanism
* bypasses any caches.
*/
-static int register_write_direct(struct target *target, unsigned number,
+static int register_write_direct(struct target *target, unsigned int number,
uint64_t value)
{
LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target),
}
/* Try to find out the widest memory access size depending on the selected memory access methods. */
-static unsigned riscv013_data_bits(struct target *target)
+static unsigned int riscv013_data_bits(struct target *target)
{
RISCV013_INFO(info);
RISCV_INFO(r);
}
static int prep_for_vector_access(struct target *target, uint64_t *vtype,
- uint64_t *vl, unsigned *debug_vl)
+ uint64_t *vl, unsigned int *debug_vl)
{
RISCV_INFO(r);
/* TODO: this continuous save/restore is terrible for performance. */
/* Write vtype and vl. */
- unsigned encoded_vsew;
+ unsigned int encoded_vsew;
switch (riscv_xlen(target)) {
case 32:
encoded_vsew = 2;
return ERROR_FAIL;
uint64_t vtype, vl;
- unsigned debug_vl;
+ unsigned int debug_vl;
if (prep_for_vector_access(target, &vtype, &vl, &debug_vl) != ERROR_OK)
return ERROR_FAIL;
- unsigned vnum = regno - GDB_REGNO_V0;
- unsigned xlen = riscv_xlen(target);
+ unsigned int vnum = regno - GDB_REGNO_V0;
+ unsigned int xlen = riscv_xlen(target);
struct riscv_program program;
riscv_program_init(&program, target);
riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));
int result = ERROR_OK;
- for (unsigned i = 0; i < debug_vl; i++) {
+ for (unsigned int i = 0; i < debug_vl; i++) {
/* Executing the program might result in an exception if there is some
* issue with the vector implementation/instructions we're using. If that
* happens, attempt to restore as usual. We may have clobbered the
return ERROR_FAIL;
uint64_t vtype, vl;
- unsigned debug_vl;
+ unsigned int debug_vl;
if (prep_for_vector_access(target, &vtype, &vl, &debug_vl) != ERROR_OK)
return ERROR_FAIL;
- unsigned vnum = regno - GDB_REGNO_V0;
- unsigned xlen = riscv_xlen(target);
+ unsigned int vnum = regno - GDB_REGNO_V0;
+ unsigned int xlen = riscv_xlen(target);
struct riscv_program program;
riscv_program_init(&program, target);
riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));
int result = ERROR_OK;
- for (unsigned i = 0; i < debug_vl; i++) {
+ for (unsigned int i = 0; i < debug_vl; i++) {
if (register_write_direct(target, GDB_REGNO_S0,
buf_get_u64(value, xlen * i, xlen)) != ERROR_OK)
return ERROR_FAIL;
}
static void log_memory_access(target_addr_t address, uint64_t value,
- unsigned size_bytes, bool read)
+ unsigned int size_bytes, bool read)
{
if (debug_level < LOG_LVL_DEBUG)
return;
static target_addr_t sb_read_address(struct target *target)
{
RISCV013_INFO(info);
- unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
+ unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
target_addr_t address = 0;
uint32_t v;
if (sbasize > 32) {
for (uint32_t i = (next_address - address) / size; i < count - 1; i++) {
for (int j = (size - 1) / 4; j >= 0; j--) {
uint32_t value;
- unsigned attempt = 0;
+ unsigned int attempt = 0;
while (1) {
if (attempt++ > 100) {
LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
uint32_t sbcs_read = 0;
if (count > 1) {
uint32_t value;
- unsigned attempt = 0;
+ unsigned int attempt = 0;
while (1) {
if (attempt++ > 100) {
LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
continue;
}
- unsigned error = get_field(sbcs_read, DM_SBCS_SBERROR);
+ unsigned int error = get_field(sbcs_read, DM_SBCS_SBERROR);
if (error == 0) {
next_address = end_address;
} else {
memset(buffer, 0, count * size);
/* Convert the size (bytes) to width (bits) */
- unsigned width = size << 3;
+ unsigned int width = size << 3;
/* Create the command (physical address, postincrement, read) */
uint32_t command = access_memory_command(target, false, width, use_aampostincrement, false);
size, address);
/* Convert the size (bytes) to width (bits) */
- unsigned width = size << 3;
+ unsigned int width = size << 3;
/* Create the command (physical address, postincrement, write) */
uint32_t command = access_memory_command(target, false, width, use_aampostincrement, true);
/* read_addr is the next address that the hart will read from, which is the
* value in s0. */
- unsigned index = 2;
+ unsigned int index = 2;
while (index < count) {
riscv_addr_t read_addr = address + index * increment;
LOG_DEBUG("i=%d, count=%d, read_addr=0x%" PRIx64, index, count, read_addr);
if (!batch)
return ERROR_FAIL;
- unsigned reads = 0;
- for (unsigned j = index; j < count; j++) {
+ unsigned int reads = 0;
+ for (unsigned int j = index; j < count; j++) {
if (size > 4)
riscv_batch_add_dmi_read(batch, DM_DATA1);
riscv_batch_add_dmi_read(batch, DM_DATA0);
return ERROR_FAIL;
info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
- unsigned next_index;
- unsigned ignore_last = 0;
+ unsigned int next_index;
+ unsigned int ignore_last = 0;
switch (info->cmderr) {
case CMDERR_NONE:
LOG_DEBUG("successful (partial?) memory read");
/* Now read whatever we got out of the batch. */
dmi_status_t status = DMI_STATUS_SUCCESS;
- unsigned read = 0;
+ unsigned int read = 0;
assert(index >= 2);
- for (unsigned j = index - 2; j < index + reads; j++) {
+ for (unsigned int j = index - 2; j < index + reads; j++) {
assert(j < count);
LOG_DEBUG("index=%d, reads=%d, next_index=%d, ignore_last=%d, j=%d",
index, reads, next_index, ignore_last, j);
goto error;
/* To write another word, we put it in S1 and execute the program. */
- unsigned start = (cur_addr - address) / size;
- for (unsigned i = start; i < count; ++i) {
- unsigned offset = size*i;
+ unsigned int start = (cur_addr - address) / size;
+ for (unsigned int i = start; i < count; ++i) {
+ unsigned int offset = size * i;
const uint8_t *t_buffer = buffer + offset;
uint64_t value = buf_get_u64(t_buffer, 0, 8 * size);
}
assert(dm->hart_count);
- unsigned hawindow_count = (dm->hart_count + 31) / 32;
+ unsigned int hawindow_count = (dm->hart_count + 31) / 32;
uint32_t hawindow[hawindow_count];
memset(hawindow, 0, sizeof(uint32_t) * hawindow_count);
target_list_t *entry;
- unsigned total_selected = 0;
+ unsigned int total_selected = 0;
list_for_each_entry(entry, &dm->target_list, list) {
struct target *t = entry->target;
struct riscv_info *r = riscv_info(t);
riscv013_info_t *info = get_info(t);
- unsigned index = info->index;
+ unsigned int index = info->index;
LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped);
r->selected = r->prepped;
if (r->prepped) {
return ERROR_OK;
}
- for (unsigned i = 0; i < hawindow_count; i++) {
+ for (unsigned int i = 0; i < hawindow_count; i++) {
if (dmi_write(target, DM_HAWINDOWSEL, i) != ERROR_OK)
return ERROR_FAIL;
if (dmi_write(target, DM_HAWINDOW, hawindow[i]) != ERROR_OK)
return RISCV_HALT_UNKNOWN;
}
-int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
+int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t data)
{
dm013_info_t *dm = get_dm(target);
if (!dm)
return ERROR_OK;
}
-riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index)
+riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index)
{
uint32_t value;
dmi_read(target, &value, DM_PROGBUF0 + index);
if (target->reg_cache->reg_list) {
free(target->reg_cache->reg_list[0].arch_info);
/* Free the ones we allocated separately. */
- for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
+ for (unsigned int i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
free(target->reg_cache->reg_list[i].arch_info);
for (unsigned int i = 0; i < target->reg_cache->num_regs; i++)
free(target->reg_cache->reg_list[i].value);
if (result != ERROR_OK)
return result;
- unsigned xlen = riscv_xlen(target);
+ unsigned int xlen = riscv_xlen(target);
mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
switch (mode) {
case SATP_MODE_SV32:
GDB_REGNO_PC,
GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
};
- for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
+ for (unsigned int i = 0; i < ARRAY_SIZE(regnums); i++) {
enum gdb_regno regno = regnums[i];
riscv_reg_t reg_value;
if (riscv_get_register(target, ®_value, regno) != ERROR_OK)
static const uint8_t *crc_code;
- unsigned xlen = riscv_xlen(target);
- unsigned crc_code_size;
+ unsigned int xlen = riscv_xlen(target);
+ unsigned int crc_code_size;
if (xlen == 32) {
crc_code = riscv32_crc_code;
crc_code_size = sizeof(riscv32_crc_code);
int halted_hart = -1;
if (target->smp) {
- unsigned should_remain_halted = 0;
- unsigned should_resume = 0;
+ unsigned int should_remain_halted = 0;
+ unsigned int should_resume = 0;
struct target_list *list;
foreach_smp_target(list, target->smp_targets) {
struct target *t = list->target;
/* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
char *arg = strtok(args, ",");
while (arg) {
- unsigned low = 0;
- unsigned high = 0;
+ unsigned int low = 0;
+ unsigned int high = 0;
char *name = NULL;
char *dash = strchr(arg, '-');
COMMAND_REGISTRATION_DONE
};
-static unsigned riscv_xlen_nonconst(struct target *target)
+static unsigned int riscv_xlen_nonconst(struct target *target)
{
return riscv_xlen(target);
}
bool riscv_supports_extension(struct target *target, char letter)
{
RISCV_INFO(r);
- unsigned num;
+ unsigned int num;
if (letter >= 'a' && letter <= 'z')
num = letter - 'a';
else if (letter >= 'A' && letter <= 'Z')
return r->misa & BIT(num);
}
-unsigned riscv_xlen(const struct target *target)
+unsigned int riscv_xlen(const struct target *target)
{
RISCV_INFO(r);
return r->xlen;
};
struct csr_info {
- unsigned number;
+ unsigned int number;
const char *name;
};
};
/* encoding.h does not contain the registers in sorted order. */
qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
- unsigned csr_info_index = 0;
+ unsigned int csr_info_index = 0;
int custom_within_range = 0;
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
r->group = "csr";
r->feature = &feature_csr;
- unsigned csr_number = number - GDB_REGNO_CSR0;
+ unsigned int csr_number = number - GDB_REGNO_CSR0;
while (csr_info[csr_info_index].number < csr_number &&
csr_info_index < ARRAY_SIZE(csr_info) - 1) {
range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
- unsigned custom_number = range->low + custom_within_range;
+ unsigned int custom_number = range->low + custom_within_range;
r->group = "custom";
r->feature = &feature_custom;
projects / users / borneoa / openocd-next.git / commitdiff