octeontx2-pf: move lmt flush to include/linux/soc

On OcteonTX2 platform CPT instruction enqueue and NIX
packet send are only possible via LMTST operations which
uses LDEOR instruction. This patch moves lmt flush
function from OcteonTX2 nic driver to include/linux/soc
since it will be used by OcteonTX2 CPT and NIC driver for
LMTST.

Signed-off-by: Suheil Chandran <schandran@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/MAINTAINERS b/MAINTAINERS
index a7e0f11def8e3398cfd01a0daffe969a54fa1481..d36bee3f1f041162c1f1c2e7e8efb2234e3369b8 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10453,6 +10453,7 @@ M:      Srujana Challa <schalla@marvell.com>
 L:     linux-crypto@vger.kernel.org
 S:     Maintained
 F:     drivers/crypto/marvell/
+F:     include/linux/soc/marvell/octeontx2/
 
 MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2)
 M:     Mirko Lindner <mlindner@marvell.com>
@@ -10525,6 +10526,7 @@ M:      hariprasad <hkelam@marvell.com>
 L:     netdev@vger.kernel.org
 S:     Supported
 F:     drivers/net/ethernet/marvell/octeontx2/nic/
+F:     include/linux/soc/marvell/octeontx2/
 
 MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER
 M:     Sunil Goutham <sgoutham@marvell.com>

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
index b18b45d02165e01450ebc0f1dd3f8adad71531c3..ceec649bdd13a9500ae9690c872304b2233ca708 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
@@ -16,6 +16,7 @@
 #include <linux/net_tstamp.h>
 #include <linux/ptp_clock_kernel.h>
 #include <linux/timecounter.h>
+#include <linux/soc/marvell/octeontx2/asm.h>
 
 #include <mbox.h>
 #include <npc.h>
@@ -462,21 +463,9 @@ static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
        return result;
 }
 
-static inline u64 otx2_lmt_flush(uint64_t addr)
-{
-       u64 result = 0;
-
-       __asm__ volatile(".cpu  generic+lse\n"
-                        "ldeor xzr,%x[rf],[%[rs]]"
-                        : [rf]"=r"(result)
-                        : [rs]"r"(addr));
-       return result;
-}
-
 #else
 #define otx2_write128(lo, hi, addr)
 #define otx2_atomic64_add(incr, ptr)           ({ *ptr += incr; })
-#define otx2_lmt_flush(addr)                   ({ 0; })
 #endif
 
 /* Alloc pointer from pool/aura */

diff --git a/include/linux/soc/marvell/octeontx2/asm.h b/include/linux/soc/marvell/octeontx2/asm.h
new file mode 100644 (file)
index 0000000..ae2279f
--- /dev/null
+++ b/include/linux/soc/marvell/octeontx2/asm.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ * Copyright (C) 2020 Marvell.
+ */
+
+#ifndef __SOC_OTX2_ASM_H
+#define __SOC_OTX2_ASM_H
+
+#if defined(CONFIG_ARM64)
+/*
+ * otx2_lmt_flush is used for LMT store operation.
+ * On octeontx2 platform CPT instruction enqueue and
+ * NIX packet send are only possible via LMTST
+ * operations and it uses LDEOR instruction targeting
+ * the coprocessor address.
+ */
+#define otx2_lmt_flush(ioaddr)                          \
+({                                                      \
+       u64 result = 0;                                 \
+       __asm__ volatile(".cpu  generic+lse\n"          \
+                        "ldeor xzr, %x[rf], [%[rs]]"   \
+                        : [rf]"=r" (result)            \
+                        : [rs]"r" (ioaddr));           \
+       (result);                                       \
+})
+#else
+#define otx2_lmt_flush(ioaddr)          ({ 0; })
+#endif
+
+#endif /* __SOC_OTX2_ASM_H */