]> www.infradead.org Git - users/hch/misc.git/commitdiff
drm/i915/psr: Deactivate PSR only on LNL and when selective fetch enabled
authorJouni Högander <jouni.hogander@intel.com>
Mon, 22 Sep 2025 10:27:25 +0000 (13:27 +0300)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 15 Oct 2025 14:12:43 +0000 (10:12 -0400)
Using intel_psr_exit in frontbuffer flush on older platforms seems to be
causing problems.

Sending single full frame update using intel_psr_force_update is anyways
more optimal compared to psr deactivate/activate -> move back to this
approach on PSR1, PSR HW tracking and Panel Replay full frame update and
use deactivate/activate only on LunarLake and only when selective fetch is
enabled.

Tested-by: Lemen <lemen@lemen.xyz>
Tested-by: Koos Vriezen <koos.vriezen@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14946
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250922102725.2752742-1-jouni.hogander@intel.com
(cherry picked from commit 924adb0bbdd8fef25fd229c76e3f602c3e8752ee)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/display/intel_psr.c

index 01bf304c705fec437485c34c12c85e43189659d4..10eb93a34cf2e5e789d827a185607fc6dcb2d7ee 100644 (file)
@@ -3402,6 +3402,7 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
        struct intel_display *display = to_intel_display(intel_dp);
 
        if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
+               /* Selective fetch prior LNL */
                if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
                        /* can we turn CFF off? */
                        if (intel_dp->psr.busy_frontbuffer_bits == 0)
@@ -3420,12 +3421,19 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
                intel_psr_configure_full_frame_update(intel_dp);
 
                intel_psr_force_update(intel_dp);
+       } else if (!intel_dp->psr.psr2_sel_fetch_enabled) {
+               /*
+                * PSR1 on all platforms
+                * PSR2 HW tracking
+                * Panel Replay Full frame update
+                */
+               intel_psr_force_update(intel_dp);
        } else {
+               /* Selective update LNL onwards */
                intel_psr_exit(intel_dp);
        }
 
-       if ((!intel_dp->psr.psr2_sel_fetch_enabled || DISPLAY_VER(display) >= 20) &&
-           !intel_dp->psr.busy_frontbuffer_bits)
+       if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
                queue_work(display->wq.unordered, &intel_dp->psr.work);
 }