Modifications for 1.1.5:
======================================================================
+* Patch by Jonathan De Bruyne, 01 Feb 2002:
+ Add support for Siemens IAD210 board
+
* Implement system call mechanism thus removing function pointers
from the bdinfo and initial_data structures.
E: obrown@adventnetworks.com
D: Port to the gw8260 board
+N: Jonathan De Bruyne
+E: jonathan.debruyne@siemens.atea.be
+D: Port to Siemens IAD210 board
+
N: Conn Clark
E: clark@esteem.com
D: ESTEEM192E support
ADS860 AMX860 c2mon CCM \
cogent_mpc8xx ESTEEM192E ETX094 FADS823 \
FADS850SAR FADS860T FLAGADM FPS850L \
- GENIETV GTH hermes ICU862 \
- IP860 IVML24 IVML24_128 IVML24_256 \
- IVMS8 IVMS8_128 IVMS8_256 LANTEC \
- lwmon MBX MBX860T MHPC \
- NX823 pcu_e RPXClassic RPXlite \
- SM850 SPD823TS SXNI855T TQM823L \
- TQM823L_LCD TQM850L TQM855L TQM860L \
- TQM860L_FEC \
+ GENIETV GTH hermes IAD210 \
+ ICU862 IP860 IVML24 IVML24_128 \
+ IVML24_256 IVMS8 IVMS8_128 IVMS8_256 \
+ LANTEC lwmon MBX MBX860T \
+ MHPC NX823 pcu_e RPXClassic \
+ RPXlite SM850 SPD823TS SXNI855T \
+ TQM823L TQM823L_LCD TQM850L TQM855L \
+ TQM860L TQM860L_FEC \
"
#########################################################################
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+IAD210_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd ./include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = IAD210" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "VENDOR = siemens" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
ICU862_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Paul Geerinckx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include "mpc8xx.h"
+#include "atm.h"
+#include "i2c.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+/* used PLD registers */
+# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
+# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
+# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
+# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
+# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
+ _NOT_USED_,
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0xFFFAF834, 0xFFE5B435, /* last */
+ _NOT_USED_,
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+ 0xF1AAF804, 0xFFA5F447, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
+ 0xFFAFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * MRS sequence (Offset 38 in UPMA RAM)
+ */
+ 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
+ _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0xFFAFFC04, 0xFFAFFC05, /* last */
+ _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+ long int size;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+
+ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ udelay(1);
+ memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
+ udelay(1);
+
+ memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
+ udelay(1);
+ memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
+ udelay(1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ */
+ size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+
+ memctl->memc_mamr = CFG_MAMR;
+ udelay (1000);
+
+ /*
+ * Final mapping
+ */
+ memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
+ memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
+
+ udelay(10000);
+
+ /* prepare pin multiplexing for fast ethernet */
+
+ atmLoad();
+ fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
+ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
+
+
+ return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+ *addr = save[--i];
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ return (maxsize);
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ return (1);
+}
+
+void board_serial_init(void)
+{
+ ;/* nothing to do here */
+}
+
+void board_ether_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+
+ atmLoad();
+ fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
+ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
+}
+
+int board_pre_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+
+ /* configure the LED timing output pins - port A pin 4 */
+ iop->iop_papar = 0x0800;
+ iop->iop_padir = 0x0800;
+
+ /* start timer 2 for the 4hz LED blink rate */
+ timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
+ timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
+ timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
+
+ /* chip select for PLD access */
+ memctl->memc_br6 = 0x10000401;
+ memctl->memc_or6 = 0xFC000908;
+
+ /* PLD initial values ( set LEDs, remove reset on LXT) */
+
+ *PLD_GCR1_REG = 0x06;
+ *PLD_EXT_RES = 0xC0;
+ *PLD_EXT_FETH = 0x40;
+ *PLD_EXT_LED = 0xFF;
+ *PLD_EXT_X21 = 0x04;
+ return 0;
+}
+
+void board_get_enetaddr (uchar *addr)
+{
+ int i;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile cpm8xx_t *cpm = &immap->im_cpm;
+ unsigned int rccrtmp;
+
+ char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
+
+ for (i=0; i<6; i++)
+ addr[i] = default_mac_addr[i];
+
+ printf("There is an error in the i2c driver .. /n");
+ printf("You need to fix it first....../n");
+
+ rccrtmp = cpm->cp_rccr;
+ cpm->cp_rccr |= 0x0020;
+
+ i2c_reg_read(0xa0, 0);
+ printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
+ i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
+ i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
+
+ cpm->cp_rccr = rccrtmp;
+
+
+}
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o atm.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+
+#include <ppcboot.h>
+#include "mpc8xx.h"
+#include <commproc.h>
+
+#include "atm.h"
+#include <linux/stddef.h>
+
+#define SYNC __asm__("sync")
+#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
+
+#define FALSE 1
+#define TRUE 0
+#define OK 0
+#define ERROR -1
+
+struct atm_connection_t g_conn[NUM_CONNECTIONS] =
+{
+ { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
+};
+
+struct atm_driver_t g_atm =
+{
+ FALSE, /* loaded */
+ FALSE, /* started */
+ NULL, /* csram */
+ 0, /* csram_size */
+ NULL, /* am_top */
+ NULL, /* ap_top */
+ NULL, /* int_reload_ptr */
+ NULL, /* int_serv_ptr */
+ NULL, /* rbd_base_ptr */
+ NULL, /* tbd_base_ptr */
+ 0 /* linerate */
+};
+
+char csram[1024]; /* more than enough for doing nothing*/
+
+int atmLoad(void);
+void atmUnload(void);
+int atmMemInit(void);
+void atmIntInit(void);
+void atmApcInit(void);
+void atmAmtInit(void);
+void atmCpmInit(void);
+void atmUtpInit(void);
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmLoad
+ *
+ * DESCRIPTION: Basic ATM initialization.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: OK or ERROR
+ *
+ ****************************************************************************/
+int atmLoad()
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+
+ timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
+ immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
+ iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
+
+ if ( atmMemInit() != OK ) return ERROR;
+
+ atmIntInit();
+ atmApcInit();
+ atmAmtInit();
+ atmCpmInit();
+ atmUtpInit();
+
+ g_atm.loaded = TRUE;
+
+ return OK;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmUnload
+ *
+ * DESCRIPTION: Disables ATM and UTOPIA.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmUnload()
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+
+ timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
+ immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
+ iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
+ g_atm.loaded = FALSE;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmMemInit
+ *
+ * DESCRIPTION:
+ *
+ * The ATM driver uses the following resources:
+ *
+ * A. Memory in DPRAM to hold
+ *
+ * 1/ CT = Connection Table ( RCT & TCT )
+ * 2/ TCTE = Transmit Connection Table Extension
+ * 3/ MPHYPT = Multi-PHY Pointing Table
+ * 4/ APCP = APC Parameter Table
+ * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
+ * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
+ * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
+ * 8/ TQ = Transmit Queue
+ * 9/ AM = Address Matching Table
+ * 10/ AP = Address Pointing Table
+ *
+ * B. Memory in cache safe RAM to hold
+ *
+ * 1/ INT = Interrupt Queue
+ * 2/ RBD = Receive Buffer Descriptors
+ * 3/ TBD = Transmit Buffer Descriptors
+ *
+ * This function
+ * 1. clears the ATM DPRAM area,
+ * 2. Allocates and clears cache safe memory,
+ * 3. Initializes 'g_conn'.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: OK or ERROR
+ *
+ ****************************************************************************/
+int atmMemInit()
+{
+ int i;
+ unsigned immr = CFG_IMMR;
+ int total_num_rbd = 0;
+ int total_num_tbd = 0;
+
+ memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
+
+ g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
+
+ for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
+ total_num_rbd += g_conn[i].num_rbd;
+ total_num_tbd += g_conn[i].num_tbd;
+ }
+
+ g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
+
+ g_atm.csram = &csram[0];
+ memset(&(g_atm.csram), 0x00, g_atm.csram_size);
+
+ g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4);
+ g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
+ g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
+
+ g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
+ g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
+ g_conn[0].ct_ptr = CT_PTR(immr);
+ g_conn[0].tcte_ptr = TCTE_PTR(immr);
+
+ return OK;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmIntInit
+ *
+ * DESCRIPTION:
+ *
+ * Initialization of the MPC860 ESAR Interrupt Queue.
+ * This function
+ * - clears all entries in the INT,
+ * - sets the WRAP bit of the last INT entry,
+ * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
+ * to the first INT entry.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARKS:
+ *
+ * - The INT resides in external cache safe memory.
+ * - The base address of the INT is stored in g_atm.int_reload_ptr.
+ * - The number of entries in the INT is given by NUM_INT_ENTRIES.
+ * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
+ *
+ ****************************************************************************/
+void atmIntInit()
+{
+ int i;
+ for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
+ g_atm.int_reload_ptr[i] = INT_WRAP;
+ g_atm.int_serv_ptr = g_atm.int_reload_ptr;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmApcInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the following ATM Pace Controller related
+ * data structures:
+ *
+ * - 1 MPHY Pointing Table (contains only one entry)
+ * - 3 APC Parameter Tables (one PHY with 3 priorities)
+ * - 3 APC Tables (one table for each priority)
+ * - 1 Transmit Queue (one transmit queue per PHY)
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmApcInit()
+{
+ int i;
+ /* unsigned immr = CFG_IMMR; */
+ uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR);
+ struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR);
+ uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR);
+ uint16 * tq_ptr = TQ_PTR(CFG_IMMR);
+ /***************************************************/
+ /* Initialize MPHY Pointing Table (only one entry) */
+ /***************************************************/
+ *mphypt_ptr = APCP_BASE;
+
+ /********************************************/
+ /* Initialize APC parameters for priority 1 */
+ /********************************************/
+ apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
+ apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
+ apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE;
+ apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
+ apcp_ptr->etqbase = TQ_BASE;
+ apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
+ apcp_ptr->etqaptr = TQ_BASE;
+ apcp_ptr->etqtptr = TQ_BASE;
+ apcp_ptr->apc_mi = 8;
+ apcp_ptr->ncits = 0x0100; /* NCITS = 1 */
+ apcp_ptr->apcnt = 0;
+ apcp_ptr->reserved1 = 0;
+ apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */
+ apcp_ptr->ptp_counter = 0;
+ apcp_ptr->ptp_txch = 0;
+ apcp_ptr->reserved2 = 0;
+
+
+ /***************************************************/
+ /* Initialize APC Tables with empty slots (0xFFFF) */
+ /***************************************************/
+ for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
+
+ /************************/
+ /* Clear Transmit Queue */
+ /************************/
+ for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmAmtInit
+ *
+ * DESCRIPTION:
+ *
+ * This function clears the first entry in the Address Matching Table and
+ * lets the first entry in the Address Pointing table point to the first
+ * entry in the TCT table (i.e. the raw cell channel).
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARKS:
+ *
+ * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
+ * RAM are initialized by atmCpmInit().
+ *
+ ****************************************************************************/
+void atmAmtInit()
+{
+ unsigned immr = CFG_IMMR;
+
+ g_atm.am_top = AM_PTR(immr);
+ g_atm.ap_top = AP_PTR(immr);
+
+ *(g_atm.ap_top--) = CT_BASE;
+ *(g_atm.am_top--) = 0;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmCpmInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the Utopia Interface Parameter RAM Map
+ * (SCC4, ATM Protocol) of the Communication Processor Modudule.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmCpmInit()
+{
+ unsigned immr = CFG_IMMR;
+
+ memset((char *)immr + 0x3F00, 0x00, 0xC0);
+
+ /*-----------------------------------------------------------------*/
+ /* RBDBASE - Receive buffer descriptors base address */
+ /* The RBDs reside in cache safe external memory. */
+ /*-----------------------------------------------------------------*/
+ *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
+
+ /*-----------------------------------------------------------------*/
+ /* SRFCR - SAR receive function code */
+ /* 0-2 rsvd = 000 */
+ /* 3-4 BO = 11 Byte ordering (big endian). */
+ /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
+ /* when the SDMA channel accesses memory. */
+ /*-----------------------------------------------------------------*/
+ *SRFCR(immr) = 0x18;
+
+ /*-----------------------------------------------------------------*/
+ /* SRSTATE - SAR receive status */
+ /* 0 EXT = 0 Extended mode off. */
+ /* 1 ACP = 0 Valid only if EXT = 1. */
+ /* 2 EC = 0 Standard 53-byte ATM cell. */
+ /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */
+ /* 4 ESAR = 1 Enhanced SAR functionality enabled. */
+ /* 5 MCF = 1 Management Cell Filter active. */
+ /* 6 SER = 0 UTOPIA mode. */
+ /* 7 MPY = 1 Multiple PHY mode. */
+ /*-----------------------------------------------------------------*/
+ *SRSTATE(immr) = 0x0D;
+
+ /*-----------------------------------------------------------------*/
+ /* MRBLR - Maximum receive buffer length register. */
+ /* Must be cleared for ATM operation (see also SMRBLR). */
+ /*-----------------------------------------------------------------*/
+ *MRBLR(immr) = 0;
+
+ /*-----------------------------------------------------------------*/
+ /* RSTATE - SCC internal receive state parameters */
+ /* The first byte must be initialized with the value of SRFCR. */
+ /*-----------------------------------------------------------------*/
+ *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
+
+ /*-----------------------------------------------------------------*/
+ /* STFCR - SAR transmit function code */
+ /* 0-2 rsvd = 000 */
+ /* 3-4 BO = 11 Byte ordering (big endian). */
+ /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
+ /* when the SDMA channel accesses memory. */
+ /*-----------------------------------------------------------------*/
+ *STFCR(immr) = 0x18;
+
+ /*-----------------------------------------------------------------*/
+ /* SRSTATE - SAR transmit status */
+ /* 0 EXT = 0 : Extended mode off */
+ /* 1 rsvd = 0 : */
+ /* 2 EC = 0 : Standard 53-byte ATM cell */
+ /* 3 rsvd = 0 : */
+ /* 4 ESAR = 1 : Enhanced SAR functionality enabled */
+ /* 5 rsvd = 0 : */
+ /* 6 SER = 0 : UTOPIA mode */
+ /* 7 MPY = 1 : Multiple PHY mode */
+ /*-----------------------------------------------------------------*/
+ *STSTATE(immr) = 0x09;
+
+ /*-----------------------------------------------------------------*/
+ /* TBDBASE - Transmit buffer descriptors base address */
+ /* The TBDs reside in cache safe external memory. */
+ /*-----------------------------------------------------------------*/
+ *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
+
+ /*-----------------------------------------------------------------*/
+ /* TSTATE - SCC internal transmit state parameters */
+ /* The first byte must be initialized with the value of STFCR. */
+ /*-----------------------------------------------------------------*/
+ *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
+
+ /*-----------------------------------------------------------------*/
+ /* CTBASE - Connection table base address */
+ /* Offset from the beginning of DPRAM (64-byte aligned). */
+ /*-----------------------------------------------------------------*/
+ *CTBASE(immr) = CT_BASE;
+
+ /*-----------------------------------------------------------------*/
+ /* INTBASE - Interrupt queue base pointer. */
+ /* The interrupt queue resides in cache safe external memory. */
+ /*-----------------------------------------------------------------*/
+ *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
+
+ /*-----------------------------------------------------------------*/
+ /* INTPTR - Pointer into interrupt queue. */
+ /* Initialize to INTBASE. */
+ /*-----------------------------------------------------------------*/
+ *INTPTR(immr) = *INTBASE(immr);
+
+ /*-----------------------------------------------------------------*/
+ /* C_MASK - Constant mask for CRC32 */
+ /* Must be initialized to 0xDEBB20E3. */
+ /*-----------------------------------------------------------------*/
+ *C_MASK(immr) = 0xDEBB20E3;
+
+ /*-----------------------------------------------------------------*/
+ /* INT_ICNT - Interrupt threshold value */
+ /*-----------------------------------------------------------------*/
+ *INT_ICNT(immr) = 1;
+
+ /*-----------------------------------------------------------------*/
+ /* INT_CNT - Interrupt counter */
+ /* Initalize to INT_ICNT. Decremented for each interrupt entry */
+ /* reported in the interrupt queue. On zero an interrupt is */
+ /* signaled to the host by setting the GINT bit in the event */
+ /* register. The counter is reinitialized with INT_ICNT. */
+ /*-----------------------------------------------------------------*/
+ *INT_CNT(immr) = *INT_ICNT(immr);
+
+ /*-----------------------------------------------------------------*/
+ /* SMRBLR - SAR maximum receive buffer length register. */
+ /* Must be a multiple of 48 bytes. Common for all ATM connections. */
+ /*-----------------------------------------------------------------*/
+ *SMRBLR(immr) = SAR_RXB_SIZE;
+
+ /*-----------------------------------------------------------------*/
+ /* APCST - APC status register. */
+ /* 0 rsvd 0 */
+ /* 1-2 CSER 11 Initialize with the same value as NSER. */
+ /* 3-4 NSER 11 Next serial or UTOPIA channel. */
+ /* 5-7 rsvd 000 */
+ /* 8-10 rsvd 000 */
+ /* 11 rsvd 0 */
+ /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */
+ /* 13 DIS 0 APC disable. Must be initiazed to 0. */
+ /* 14 PL2 0 Not used. */
+ /* 15 MPY 1 Multiple PHY mode on. */
+ /*-----------------------------------------------------------------*/
+ *APCST(immr) = 0x7809;
+
+ /*-----------------------------------------------------------------*/
+ /* APCPTR - Pointer to the APC parameter table */
+ /* In MPHY master mode this parameter points to the MPHY pointing */
+ /* table. 2-byte aligned. */
+ /*-----------------------------------------------------------------*/
+ *APCPTR(immr) = MPHYPT_BASE;
+
+ /*-----------------------------------------------------------------*/
+ /* HMASK - Header mask */
+ /* Each incoming cell is masked with HMASK before being compared */
+ /* to the entries in the address matching table. */
+ /*-----------------------------------------------------------------*/
+ *HMASK(immr) = AM_HMASK;
+
+ /*-----------------------------------------------------------------*/
+ /* AMBASE - Address matching table base address */
+ /*-----------------------------------------------------------------*/
+ *AMBASE(immr) = AM_BASE;
+
+ /*-----------------------------------------------------------------*/
+ /* AMEND - Address matching table end address */
+ /*-----------------------------------------------------------------*/
+ *AMEND(immr) = AM_BASE;
+
+ /*-----------------------------------------------------------------*/
+ /* APBASE - Address pointing table base address */
+ /*-----------------------------------------------------------------*/
+ *APBASE(immr) = AP_BASE;
+
+ /*-----------------------------------------------------------------*/
+ /* MPHYST - MPHY status register */
+ /* 0-1 rsvd 00 */
+ /* 2-6 NMPHY 00000 1 PHY */
+ /* 7-9 rsvd 000 */
+ /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */
+ /*-----------------------------------------------------------------*/
+ *MPHYST(immr) = 0x0000;
+
+ /*-----------------------------------------------------------------*/
+ /* TCTEBASE - Transmit connection table extension base address */
+ /* Offset from the beginning of DPRAM (32-byte aligned). */
+ /*-----------------------------------------------------------------*/
+ *TCTEBASE(immr) = TCTE_BASE;
+
+ /*-----------------------------------------------------------------*/
+ /* Clear not used registers. */
+ /*-----------------------------------------------------------------*/
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmUtpInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the ATM interface for
+ *
+ * - UTOPIA mode
+ * - muxed bus
+ * - master operation
+ * - multi PHY (because of a bug in the MPC860P rev. E.0)
+ * - internal clock = SYSCLK / 2
+ *
+ * EXTERNAL EFFECTS:
+ *
+ * After calling this function, the MPC860ESAR UTOPIA bus is
+ * active and uses the following ports/pins:
+ *
+ * Port Pin Signal Description
+ * ------ --- ------- -------------------------------------------
+ * PB[15] R17 TxClav Transmit cell available input/output signal
+ * PC[15] D16 RxClav Receive cell available input/output signal
+ * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal
+ * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal
+ * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal
+ * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal
+ * PD[11] T16 RXENB Receive enable input/output signal
+ * PD[10] W18 TXENB Transmit enable input/output signal
+ * PD[9] V17 UTPCLK UTOPIA clock input/output signal
+ * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal
+ * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal
+ * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal
+ * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal
+ * PD[3] W16 SOC Start of cell input/output signal
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARK:
+ *
+ * The ATM parameters and data structures must be configured before
+ * initializing the UTOPIA port. The UTOPIA port activates immediately
+ * upon initialization, and if its associated data structures are not
+ * initialized, the CPM will lock up.
+ *
+ ****************************************************************************/
+void atmUtpInit()
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile car8xx_t *car = &immap->im_clkrst;
+ volatile cpm8xx_t *cpm = &immap->im_cpm;
+ int flag;
+
+ flag = disable_interrupts();
+
+ /*-----------------------------------------------------------------*/
+ /* SCCR - System Clock Control Register */
+ /* */
+ /* The UTOPIA clock can be selected to be internal clock or */
+ /* external clock (selected by the UTOPIA mode register). */
+ /* In case of internal clock, the UTOPIA clock is derived from */
+ /* the system frequency divided by two dividers. */
+ /* Bits 27-31 of the SCCR register are defined to control the */
+ /* UTOPIA clock. */
+ /* */
+ /* SCCR[27:29] DFUTP Division factor. Divide the system clock */
+ /* by 2^DFUTP. */
+ /* SCCR[30:31] DFAUTP Additional division factor. Divide the */
+ /* system clock by the following value: */
+ /* 00 = divide by 1 */
+ /* 00 = divide by 3 */
+ /* 10 = divide by 5 */
+ /* 11 = divide by 7 */
+ /* */
+ /* Note that the UTOPIA clock must be programmed as to operate */
+ /* within the range SYSCLK/10 .. 50Mhz. */
+ /*-----------------------------------------------------------------*/
+ car->car_sccr &= 0xFFFFFFE0;
+ car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
+
+ /*-----------------------------------------------------------------*/
+ /* RCCR - RISC Controller Configuration Register */
+ /* */
+ /* RCCR[8] DR1M IDMA Request 0 Mode */
+ /* 0 = edge sensitive */
+ /* 1 = level sensitive */
+ /* RCCR[9] DR0M IDMA Request 0 Mode */
+ /* 0 = edge sensitive */
+ /* 1 = level sensitive */
+ /* RCCR[10:11] DRQP IDMA Request Priority */
+ /* 00 = IDMA req. have more prio. than SCCs */
+ /* 01 = IDMA req. have less prio. then SCCs */
+ /* 10 = IDMA requests have the lowest prio. */
+ /* 11 = reserved */
+ /* */
+ /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
+ /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
+ /* higher priority. */
+ /*-----------------------------------------------------------------*/
+ cpm->cp_rccr &= 0xFF0F;
+ cpm->cp_rccr |= 0x00D0;
+
+ /*-----------------------------------------------------------------*/
+ /* Port B - TxClav Signal */
+ /*-----------------------------------------------------------------*/
+ cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
+ cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
+
+ /*-----------------------------------------------------------------*/
+ /* UTOPIA Mode Register */
+ /* */
+ /* - muxed bus (master operation only) */
+ /* - multi PHY (because of a bug in the MPC860P rev.E.0) */
+ /* - internal clock */
+ /* - no loopback */
+ /* - do no activate statistical counters */
+ /*-----------------------------------------------------------------*/
+ iop->utmode = 0x00000004; SYNC;
+
+ /*-----------------------------------------------------------------*/
+ /* Port D - UTOPIA Data and Control Signals */
+ /* */
+ /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */
+ /* 11 RXENB UTOPIA receive enable input/output signal */
+ /* 10 TXENB UTOPIA transmit enable input/output signal */
+ /* 9 TUPCLK UTOPIA clock input/output signal */
+ /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */
+ /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */
+ /* 3 SOC UTOPIA Start of cell input/output signal */
+ /* 2 Reserved */
+ /* 1 Enable UTOPIA mode */
+ /* 0 Enable SAR */
+ /*-----------------------------------------------------------------*/
+ iop->iop_pdpar |= 0xDF7F; SYNC;
+ iop->iop_pddir &= 0x2080; SYNC;
+
+ /*-----------------------------------------------------------------*/
+ /* Port C - RxClav Signal */
+ /*-----------------------------------------------------------------*/
+ iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */
+ iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */
+ iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */
+
+ if (flag)
+ enable_interrupts();
+}
--- /dev/null
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned int uint32;
+typedef volatile unsigned char vuint8;
+typedef volatile unsigned short vuint16;
+typedef volatile unsigned int vuint32;
+
+
+#define DPRAM_ATM CFG_IMMR + 0x3000
+
+#define ATM_DPRAM_BEGIN (DPRAM_ATM - CFG_IMMR - 0x2000)
+#define NUM_CONNECTIONS 1
+#define SAR_RXB_SIZE 1584
+#define AM_HMASK 0x0FFFFFF0
+
+#define NUM_CT_ENTRIES (NUM_CONNECTIONS)
+#define NUM_TCTE_ENTRIES (NUM_CONNECTIONS)
+#define NUM_AM_ENTRIES (NUM_CONNECTIONS+1)
+#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1)
+#define NUM_MPHYPT_ENTRIES 1
+#define NUM_APCP_ENTRIES 1
+#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */
+#define NUM_TQ_ENTRIES 12
+
+#define SIZE_OF_CT_ENTRY 64
+#define SIZE_OF_TCTE_ENTRY 32
+#define SIZE_OF_AM_ENTRY 4
+#define SIZE_OF_AP_ENTRY 2
+#define SIZE_OF_MPHYPT_ENTRY 2
+#define SIZE_OF_APCP_ENTRY 32
+#define SIZE_OF_APCT_ENTRY 2
+#define SIZE_OF_TQ_ENTRY 2
+
+#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64*/
+#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32*/
+#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32*/
+#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4*/
+#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
+#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2*/
+#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
+#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2*/
+#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2*/
+#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2*/
+#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
+
+#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
+#define TCTE_PTR(base) ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
+#define AM_PTR(base) ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
+#define AP_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
+#define MPHYPT_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
+#define APCP_PTR(base) ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
+#define APCT1_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
+#define APCT2_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
+#define APCT3_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
+#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
+
+/* SAR registers */
+#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */
+#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */
+#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */
+#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */
+#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */
+#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */
+#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */
+#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */
+#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */
+#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */
+#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */
+#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */
+#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */
+#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */
+#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */
+#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */
+#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */
+#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */
+#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */
+#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */
+#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */
+#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */
+#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */
+#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */
+#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */
+#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */
+#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */
+#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */
+#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */
+#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */
+#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */
+#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */
+#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */
+#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */
+#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */
+#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */
+#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */
+#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */
+#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */
+#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */
+#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */
+#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */
+#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */
+#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */
+#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */
+
+/* ESAR registers */
+#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */
+#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */
+#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */
+#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */
+#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */
+#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */
+#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */
+#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */
+#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */
+
+/* UTOPIA Mode Register */
+#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978))
+
+/* SAR commands */
+#define TRANSMIT_CHANNEL_ACTIVATE_CMD 0x0FC1
+#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
+#define STOP_TRANSMIT_CMD 0x2FC1
+#define RESTART_TRANSMIT_CMD 0x3FC1
+#define STOP_RECEIVE_CMD 0x4FC1
+#define RESTART_RECEIVE_CMD 0x5FC1
+#define APC_BYPASS_CMD 0x6FC1
+#define MEM_WRITE_CMD 0x7FC1
+#define CPCR_FLG 0x0001
+
+/* INT flags */
+#define INT_VALID 0x80000000
+#define INT_WRAP 0x40000000
+#define INT_APCO 0x00800000
+#define INT_TQF 0x00200000
+#define INT_RXF 0x00080000
+#define INT_BSY 0x00040000
+#define INT_TXB 0x00020000
+#define INT_RXB 0x00010000
+
+#define NUM_INT_ENTRIES 80
+#define SIZE_OF_INT_ENTRY 4
+
+struct apc_params_t
+{
+ vuint16 apct_base1; /* APC Table - First Priority Base pointer */
+ vuint16 apct_end1; /* First APC Table - Length */
+ vuint16 apct_ptr1; /* First APC Table Pointer */
+ vuint16 apct_sptr1; /* APC Table First Priority Service pointer */
+ vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */
+ vuint16 etqend; /* Enhanced Transmit Queue End pointer */
+ vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */
+ vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */
+ vuint16 apc_mi; /* APC - Max Iteration */
+ vuint16 ncits; /* Number of Cells In TimeSlot */
+ vuint16 apcnt; /* APC - N Timer */
+ vuint16 reserved1; /* reserved */
+ vuint16 eapcst; /* APC status */
+ vuint16 ptp_counter; /* PTP queue length */
+ vuint16 ptp_txch; /* PTP channel */
+ vuint16 reserved2; /* reserved */
+};
+
+struct ct_entry_t
+{
+ /* RCT */
+ unsigned fhnt : 1;
+ unsigned pm_rct : 1;
+ unsigned reserved0 : 6;
+ unsigned hec : 1;
+ unsigned clp : 1;
+ unsigned cng_ncrc : 1;
+ unsigned inf_rct : 1;
+ unsigned cngi_ptp : 1;
+ unsigned cdis_rct : 1;
+ unsigned aal_rct : 2;
+ uint16 rbalen;
+ uint32 rcrc;
+ uint32 rb_ptr;
+ uint16 rtmlen;
+ uint16 rbd_ptr;
+ uint16 rbase;
+ uint16 tstamp;
+ uint16 imask;
+ unsigned ft : 2;
+ unsigned nim : 1;
+ unsigned reserved1 : 2;
+ unsigned rpmt : 6;
+ unsigned reserved2 : 5;
+ uint8 reserved3[8];
+ /* TCT */
+ unsigned reserved4 : 1;
+ unsigned pm_tct : 1;
+ unsigned reserved5 : 6;
+ unsigned pc : 1;
+ unsigned reserved6 : 2;
+ unsigned inf_tct : 1;
+ unsigned cr10 : 1;
+ unsigned cdis_tct : 1;
+ unsigned aal_tct : 2;
+ uint16 tbalen;
+ uint32 tcrc;
+ uint32 tb_ptr;
+ uint16 ttmlen;
+ uint16 tbd_ptr;
+ uint16 tbase;
+ unsigned reserved7 : 5;
+ unsigned tpmt : 6;
+ unsigned reserved8 : 3;
+ unsigned avcf : 1;
+ unsigned act : 1;
+ uint32 chead;
+ uint16 apcl;
+ uint16 apcpr;
+ unsigned out : 1;
+ unsigned bnr : 1;
+ unsigned tservice : 2;
+ unsigned apcp : 12;
+ uint16 apcpf;
+};
+
+struct tcte_entry_t
+{
+ unsigned res1 : 4;
+ unsigned scr : 12;
+ uint16 scrf;
+ uint16 bt;
+ uint16 buptrh;
+ uint32 buptrl;
+ unsigned vbr2 : 1;
+ unsigned res2 : 15;
+ uint16 oobr;
+ uint16 res3[8];
+};
+
+#define SIZE_OF_RBD 12
+#define SIZE_OF_TBD 12
+
+struct atm_bd_t
+{
+ vuint16 flags;
+ vuint16 length;
+ unsigned char * buffer_ptr;
+ vuint16 cpcs_uu_cpi;
+ vuint16 reserved;
+};
+
+/* BD flags */
+#define EMPTY 0x8000
+#define READY 0x8000
+#define WRAP 0x2000
+#define INTERRUPT 0x1000
+#define LAST 0x0800
+#define FIRST 0x0400
+#define OAM 0x0400
+#define CONTINUOUS 0x0200
+#define HEC_ERROR 0x0080
+#define CELL_LOSS 0x0040
+#define CONGESTION 0x0020
+#define ABORT 0x0010
+#define LEN_ERROR 0x0002
+#define CRC_ERROR 0x0001
+
+struct atm_connection_t
+{
+ struct atm_bd_t * rbd_ptr;
+ int num_rbd;
+ struct atm_bd_t * tbd_ptr;
+ int num_tbd;
+ struct ct_entry_t * ct_ptr;
+ struct tcte_entry_t * tcte_ptr;
+ void * drv;
+ void (* notify)(void * drv, int event);
+};
+
+struct atm_driver_t
+{
+ int loaded;
+ int started;
+ char * csram;
+ int csram_size;
+ uint32 * am_top;
+ uint16 * ap_top;
+ uint32 * int_reload_ptr;
+ uint32 * int_serv_ptr;
+ struct atm_bd_t * rbd_base_ptr;
+ struct atm_bd_t * tbd_base_ptr;
+ unsigned linerate_in_bps;
+};
+
+extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
+extern struct atm_driver_t g_atm;
+
+extern int atmLoad(void);
+extern void atmUnload(void);
--- /dev/null
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# iad210 boards
+#
+
+TEXT_BASE = 0x08000000
+//TEXT_BASE = 0x00200000
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00900090;
+
+ value = addr[0];
+
+ switch (value) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+ case AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#if 0 /* enable when device IDs are available */
+ case AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned long *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (volatile unsigned long *)info->start[0];
+
+ *addr = 0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00800080;
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_long*)(info->start[sect]);
+ addr[0] = 0x00300030;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_long*)(info->start[l_sect]);
+ while ((addr[0] & 0x00800080) != 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned long *)info->start[0];
+ addr[0] = 0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00A000A0;
+
+ *((vu_long *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/ppcstring.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ ppc/time.o (.text)
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
i = getenv_r ("ethaddr", tmp, sizeof(tmp));
s = (i > 0) ? tmp : NULL;
-#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC)
+#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210)
if (s == NULL)
board_get_enetaddr(bd->bi_enetaddr);
else
busfreq = (bd->bi_busfreq * 1000000 + 4999999) / 5000000;
fecp->fec_mii_speed = ((busfreq * 1000000) / 2500000) & 0x7e;
-#if !defined(CONFIG_ICU862)
+#if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
/* Configure all of port D for MII.
*/
immr->im_ioport.iop_pdpar = 0x1fff;
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_phyaddr(phyno));
+#ifdef ET_DEBUG
+ printf("PHY type 0x%x pass %d type ", phytype, pass);
+#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
#endif /* CONFIG_HERMES */
+/*** IAD210 **********************************************************/
+
+/* The IAD210 uses the FEC on a MPC860P for Ethernet */
+
+#if defined(CONFIG_IAD210)
+
+# define FEC_ENET /* use FEC for Ethernet */
+# undef SCC_ENET
+
+# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
+# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
+# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
+# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
+# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
+# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
+# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
+# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
+# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
+# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
+# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
+# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
+# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
+
+# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
+
+#endif /* CONFIG_IAD210 */
+
/*** ICU862 **********************************************************/
#if defined(CONFIG_ICU862)
--- /dev/null
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <mpc8xx_irq.h>
+
+
+# ifdef DEBUG
+# warning DEBUG Defined
+# endif /* DEBUG */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC860 1
+#define CONFIG_IAD210 1 /* ...on a IAD210 module */
+#define CONFIG_MPC860T 1
+#define CONFIG_MPC862 1
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+
+#undef CONFIG_8xx_CONS_SMC1
+#undef CONFIG_8xx_CONS_SMC2
+#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 9600
+
+
+# define MPC8XX_FACT 16
+# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if cant use get_gclk_freq */
+# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#if 0
+# define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+/* using this define saves us updating another source file */
+#define CONFIG_BOARD_PRE_INIT 1
+
+#undef CONFIG_BOOTARGS
+/* #define CONFIG_BOOTCOMMAND \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "bootm"
+*/
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs" \
+ "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
+# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+# define CFG_DISCOVER_PHY 1
+# define CONFIG_FEC_UTOPIA 1
+# define CONFIG_ETHADDR 08:00:06:26:A2:6D
+# define CONFIG_IPADDR 192.168.28.128
+# define CONFIG_SERVERIP 139.10.137.138
+# define CFG_DISCOVER_PHY 1
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_I2C
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xDD
+
+#if 0
+#define CONFIG_SOFT_I2C /* Software I2C support enabled */
+# define CFG_I2C_SPEED 50000
+# define CFG_I2C_SLAVE 0xFE
+# define CFG_I2C_EEPROM_ADDR 0x50
+#endif
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+#define CFG_IMMR_SIZE ((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x08000000
+#define CFG_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#if defined(DEBUG)
+# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#endif
+
+# define CFG_MONITOR_BASE CFG_FLASH_BASE
+# define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+
+#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
+ SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
+ SCCR_DFLCD000 |SCCR_DFALCD00 )
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register 19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
+#define CFG_RCCR 0x0020
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCMCIA_MEM_ADDR ((uint)0xff020000)
+#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently. Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register. For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0xF8000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xF8000000 /* OR addr mask */
+
+/* FLASH timing:
+ TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
+ OR_SCY_3_CLK | OR_EHTR)
+
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4)
+#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA 124 /* start with divider for 64 MHz */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLB_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+
+#endif /* __CONFIG_H */
#ifdef CONFIG_RPXCLASSIC
void rpxclassic_init (void);
-void board_get_enetaddr (uchar *addr);
#endif
#ifdef CONFIG_MBX
/* $(BOARD)/mbx8xx.c */
void mbx_init (void);
-void board_get_enetaddr (uchar *addr);
void board_serial_init (void);
void board_ether_init (void);
#endif
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || defined(CONFIG_IAD210)
+void board_get_enetaddr (uchar *addr);
+#endif
+
#ifdef CONFIG_HERMES
/* $(BOARD)/hermes.c */
void hermes_start_lxt980 (int speed);
projects / users / rw / ppcboot.git / commitdiff