int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
                              enum cs35l41_cspl_mbox_cmd cmd);
 int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap);
+int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap);
 int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
                       struct cs35l41_hw_cfg *hw_cfg);
 bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type);
 
 }
 EXPORT_SYMBOL_GPL(cs35l41_write_fs_errata);
 
+static void cs35l41_wait_for_pwrmgt_sts(struct device *dev, struct regmap *regmap)
+{
+       const int pwrmgt_retries = 10;
+       unsigned int sts;
+       int i, ret;
+
+       for (i = 0; i < pwrmgt_retries; i++) {
+               ret = regmap_read(regmap, CS35L41_PWRMGT_STS, &sts);
+               if (ret)
+                       dev_err(dev, "Failed to read PWRMGT_STS: %d\n", ret);
+               else if (!(sts & CS35L41_WR_PEND_STS_MASK))
+                       return;
+
+               udelay(20);
+       }
+
+       dev_err(dev, "Timed out reading PWRMGT_STS\n");
+}
+
+int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap)
+{
+       const int wake_retries = 20;
+       const int sleep_retries = 5;
+       int ret, i, j;
+
+       for (i = 0; i < sleep_retries; i++) {
+               dev_dbg(dev, "Exit hibernate\n");
+
+               for (j = 0; j < wake_retries; j++) {
+                       ret = cs35l41_set_cspl_mbox_cmd(dev, regmap,
+                                                       CSPL_MBOX_CMD_OUT_OF_HIBERNATE);
+                       if (!ret)
+                               break;
+
+                       usleep_range(100, 200);
+               }
+
+               if (j < wake_retries) {
+                       dev_dbg(dev, "Wake success at cycle: %d\n", j);
+                       return 0;
+               }
+
+               dev_err(dev, "Wake failed, re-enter hibernate: %d\n", ret);
+
+               cs35l41_wait_for_pwrmgt_sts(dev, regmap);
+               regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088);
+
+               cs35l41_wait_for_pwrmgt_sts(dev, regmap);
+               regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188);
+
+               cs35l41_wait_for_pwrmgt_sts(dev, regmap);
+               regmap_write(regmap, CS35L41_PWRMGT_CTL, 0x3);
+       }
+
+       dev_err(dev, "Timed out waking device\n");
+
+       return -ETIMEDOUT;
+}
+EXPORT_SYMBOL_GPL(cs35l41_exit_hibernate);
+
 MODULE_DESCRIPTION("CS35L41 library");
 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
 MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>");
 
        return 0;
 }
 
-static void cs35l41_wait_for_pwrmgt_sts(struct cs35l41_private *cs35l41)
-{
-       const int pwrmgt_retries = 10;
-       unsigned int sts;
-       int i, ret;
-
-       for (i = 0; i < pwrmgt_retries; i++) {
-               ret = regmap_read(cs35l41->regmap, CS35L41_PWRMGT_STS, &sts);
-               if (ret)
-                       dev_err(cs35l41->dev, "Failed to read PWRMGT_STS: %d\n", ret);
-               else if (!(sts & CS35L41_WR_PEND_STS_MASK))
-                       return;
-
-               udelay(20);
-       }
-
-       dev_err(cs35l41->dev, "Timed out reading PWRMGT_STS\n");
-}
-
-static int cs35l41_exit_hibernate(struct cs35l41_private *cs35l41)
-{
-       const int wake_retries = 20;
-       const int sleep_retries = 5;
-       int ret, i, j;
-
-       for (i = 0; i < sleep_retries; i++) {
-               dev_dbg(cs35l41->dev, "Exit hibernate\n");
-
-               for (j = 0; j < wake_retries; j++) {
-                       ret = cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
-                                                       CSPL_MBOX_CMD_OUT_OF_HIBERNATE);
-                       if (!ret)
-                               break;
-
-                       usleep_range(100, 200);
-               }
-
-               if (j < wake_retries) {
-                       dev_dbg(cs35l41->dev, "Wake success at cycle: %d\n", j);
-                       return 0;
-               }
-
-               dev_err(cs35l41->dev, "Wake failed, re-enter hibernate: %d\n", ret);
-
-               cs35l41_wait_for_pwrmgt_sts(cs35l41);
-               regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0088);
-
-               cs35l41_wait_for_pwrmgt_sts(cs35l41);
-               regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0188);
-
-               cs35l41_wait_for_pwrmgt_sts(cs35l41);
-               regmap_write(cs35l41->regmap, CS35L41_PWRMGT_CTL, 0x3);
-       }
-
-       dev_err(cs35l41->dev, "Timed out waking device\n");
-
-       return -ETIMEDOUT;
-}
-
 static int __maybe_unused cs35l41_runtime_resume(struct device *dev)
 {
        struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
 
        regcache_cache_only(cs35l41->regmap, false);
 
-       ret = cs35l41_exit_hibernate(cs35l41);
+       ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
        if (ret)
                return ret;