perf arm64: Sync ESR_ELx_EC_* macros in arm64_exception_types.h with esr.h

Update perf util arm64_exception_types.h to match the exception class
macros defined in tools/arch/arm64/include/asm/esr.h.

This ensures consistency between perf tooling and the kernel header
definitions for ESR_ELx_EC_* values.

In v2, ESR_ELx_EC_OTHER and ESR_ELx_EC_GCS, which were missing in v1, were
included.

Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yunseong Kim <ysk@kzalloc.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linux.dev>
Cc: Levi Yun <yeoreum.yun@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20250822145855.53071-2-ysk@kzalloc.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/arch/arm64/util/arm64_exception_types.h b/tools/perf/arch/arm64/util/arm64_exception_types.h
index 27c981ebe401228e077257805bd78b6f9069d938..bf827f19ace0d1bab3a9720c487c95fde8374dd0 100644 (file)
--- a/tools/perf/arch/arm64/util/arm64_exception_types.h
+++ b/tools/perf/arch/arm64/util/arm64_exception_types.h
@@ -31,9 +31,10 @@
 #define ESR_ELx_EC_FP_ASIMD    (0x07)
 #define ESR_ELx_EC_CP10_ID     (0x08)  /* EL2 only */
 #define ESR_ELx_EC_PAC         (0x09)  /* EL2 and above */
-/* Unallocated EC: 0x0A - 0x0B */
+#define ESR_ELx_EC_OTHER       (0x0A)
+/* Unallocated EC: 0x0B */
 #define ESR_ELx_EC_CP14_64     (0x0C)
-/* Unallocated EC: 0x0d */
+#define ESR_ELx_EC_BTI         (0x0D)
 #define ESR_ELx_EC_ILL         (0x0E)
 /* Unallocated EC: 0x0F - 0x10 */
 #define ESR_ELx_EC_SVC32       (0x11)
@@ -46,7 +47,10 @@
 #define ESR_ELx_EC_SYS64       (0x18)
 #define ESR_ELx_EC_SVE         (0x19)
 #define ESR_ELx_EC_ERET                (0x1a)  /* EL2 only */
-/* Unallocated EC: 0x1b - 0x1E */
+/* Unallocated EC: 0x1B */
+#define ESR_ELx_EC_FPAC                (0x1C)  /* EL1 and above */
+#define ESR_ELx_EC_SME         (0x1D)
+/* Unallocated EC: 0x1E */
 #define ESR_ELx_EC_IMP_DEF     (0x1f)  /* EL3 only */
 #define ESR_ELx_EC_IABT_LOW    (0x20)
 #define ESR_ELx_EC_IABT_CUR    (0x21)
@@ -55,11 +59,12 @@
 #define ESR_ELx_EC_DABT_LOW    (0x24)
 #define ESR_ELx_EC_DABT_CUR    (0x25)
 #define ESR_ELx_EC_SP_ALIGN    (0x26)
-/* Unallocated EC: 0x27 */
+#define ESR_ELx_EC_MOPS                (0x27)
 #define ESR_ELx_EC_FP_EXC32    (0x28)
 /* Unallocated EC: 0x29 - 0x2B */
 #define ESR_ELx_EC_FP_EXC64    (0x2C)
-/* Unallocated EC: 0x2D - 0x2E */
+#define ESR_ELx_EC_GCS         (0x2D)
+/* Unallocated EC: 0x2E */
 #define ESR_ELx_EC_SERROR      (0x2F)
 #define ESR_ELx_EC_BREAKPT_LOW (0x30)
 #define ESR_ELx_EC_BREAKPT_CUR (0x31)