*active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_NDR;
                break;
+       case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):
+               *active_width = IB_WIDTH_8X;
+               *active_speed = IB_SPEED_NDR;
+               break;
        default:
                return -EINVAL;
        }
 
        [MLX5E_100GAUI_1_100GBASE_CR_KR] = 100000,
        [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000,
        [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000,
+       [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000,
 };
 
 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
 
        MLX5E_200GAUI_2_200GBASE_CR2_KR2        = 13,
        MLX5E_400GAUI_8                         = 15,
        MLX5E_400GAUI_4_400GBASE_CR4_KR4        = 16,
+       MLX5E_800GAUI_8_800GBASE_CR8_KR8        = 19,
        MLX5E_EXT_LINK_MODES_NUMBER,
 };