priv->config.pes = priv->hwconfig.hwnumpes;
        priv->config.rings = min_t(u32, priv->hwconfig.hwnumrings, max_rings);
+       /* Cannot currently support more rings than we have ring AICs! */
+       priv->config.rings = min_t(u32, priv->config.rings,
+                                       priv->hwconfig.hwnumraic);
 
        priv->config.cd_size = EIP197_CD64_FETCH_SIZE;
        priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask;
                                            EIP197_N_RINGS_MASK;
        }
 
+       /* Scan for ring AIC's */
+       for (i = 0; i < EIP197_MAX_RING_AIC; i++) {
+               version = readl(EIP197_HIA_AIC_R(priv) +
+                               EIP197_HIA_AIC_R_VERSION(i));
+               if (EIP197_REG_LO16(version) != EIP201_VERSION_LE)
+                       break;
+       }
+       priv->hwconfig.hwnumraic = i;
+
        /* Get supported algorithms from EIP96 transform engine */
        priv->hwconfig.algo_flags = readl(EIP197_PE(priv) +
                                    EIP197_PE_EIP96_OPTIONS(0));
        /* Print single info line describing what we just detected */
        dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x,alg:%08x\n",
                 peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hwnumpes,
-                priv->hwconfig.hwnumrings, priv->hwconfig.hiaver,
-                priv->hwconfig.hwdataw, priv->hwconfig.hwcfsize,
-                priv->hwconfig.hwrfsize, priv->hwconfig.pever,
-                priv->hwconfig.algo_flags);
+                priv->hwconfig.hwnumrings, priv->hwconfig.hwnumraic,
+                priv->hwconfig.hiaver, priv->hwconfig.hwdataw,
+                priv->hwconfig.hwcfsize, priv->hwconfig.hwrfsize,
+                priv->hwconfig.pever, priv->hwconfig.algo_flags);
 
        safexcel_configure(priv);
 
 
 #define EIP97_VERSION_LE                       0x9e61
 #define EIP197_VERSION_LE                      0x3ac5
 #define EIP96_VERSION_LE                       0x9f60
+#define EIP201_VERSION_LE                      0x36c9
 #define EIP197_REG_LO16(reg)                   (reg & 0xffff)
 #define EIP197_REG_HI16(reg)                   ((reg >> 16) & 0xffff)
 #define EIP197_VERSION_MASK(reg)               ((reg >> 16) & 0xfff)
 #define EIP197_MAX_RINGS                       4
 #define EIP197_FETCH_DEPTH                     2
 #define EIP197_MAX_BATCH_SZ                    64
+#define EIP197_MAX_RING_AIC                    14
 
 #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
                                 GFP_KERNEL : GFP_ATOMIC)
 #define EIP197_HIA_AIC_R_ENABLED_STAT(r)       (0xe010 - EIP197_HIA_AIC_R_OFF(r))
 #define EIP197_HIA_AIC_R_ACK(r)                        (0xe010 - EIP197_HIA_AIC_R_OFF(r))
 #define EIP197_HIA_AIC_R_ENABLE_CLR(r)         (0xe014 - EIP197_HIA_AIC_R_OFF(r))
+#define EIP197_HIA_AIC_R_VERSION(r)            (0xe01c - EIP197_HIA_AIC_R_OFF(r))
 #define EIP197_HIA_AIC_G_ENABLE_CTRL           0xf808
 #define EIP197_HIA_AIC_G_ENABLED_STAT          0xf810
 #define EIP197_HIA_AIC_G_ACK                   0xf810
        int hwrfsize;
        int hwnumpes;
        int hwnumrings;
+       int hwnumraic;
 };
 
 struct safexcel_crypto_priv {