drm/i915/display: Add power well mapping for WCL

WCL has 3 pipes and two TC ports, create power well mapping to reflect
HW. Rest remains similar to Xe3 power well configuration.

v2: Remove TC3/4 ports as they do not exist.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250808081931.4101388-1-chaitanya.kumar.borah@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 77268802b55eda64db1ad7997f8c7fdb15fdb9e2..39b71fffa2cd71c39eb84772b1965b4ab8c66cef 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1717,6 +1717,59 @@ static const struct i915_power_well_desc_list xe3lpd_power_wells[] = {
        I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
 };
 
+static const struct i915_power_well_desc wcl_power_wells_main[] = {
+       {
+               .instances = &I915_PW_INSTANCES(
+                       I915_PW("PW_2", &xe3lpd_pwdoms_pw_2,
+                               .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+                               .id = SKL_DISP_PW_2),
+               ),
+               .ops = &hsw_power_well_ops,
+               .has_vga = true,
+               .has_fuses = true,
+       }, {
+               .instances = &I915_PW_INSTANCES(
+                       I915_PW("PW_A", &xelpd_pwdoms_pw_a,
+                               .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
+               ),
+               .ops = &hsw_power_well_ops,
+               .irq_pipe_mask = BIT(PIPE_A),
+               .has_fuses = true,
+       }, {
+               .instances = &I915_PW_INSTANCES(
+                       I915_PW("PW_B", &xe3lpd_pwdoms_pw_b,
+                               .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
+               ),
+               .ops = &hsw_power_well_ops,
+               .irq_pipe_mask = BIT(PIPE_B),
+               .has_fuses = true,
+       }, {
+               .instances = &I915_PW_INSTANCES(
+                       I915_PW("PW_C", &xe3lpd_pwdoms_pw_c,
+                               .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
+               ),
+               .ops = &hsw_power_well_ops,
+               .irq_pipe_mask = BIT(PIPE_C),
+               .has_fuses = true,
+       }, {
+               .instances = &I915_PW_INSTANCES(
+                       I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
+                       I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
+                       I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
+                       I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
+               ),
+               .ops = &xelpdp_aux_power_well_ops,
+       },
+};
+
+static const struct i915_power_well_desc_list wcl_power_wells[] = {
+       I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+       I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+       I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff),
+       I915_PW_DESCRIPTORS(wcl_power_wells_main),
+       I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
 static void init_power_well_domains(const struct i915_power_well_instance *inst,
                                    struct i915_power_well *power_well)
 {
@@ -1824,7 +1877,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
                return 0;
        }
 
-       if (DISPLAY_VER(display) >= 30)
+       if (DISPLAY_VERx100(display) == 3002)
+               return set_power_wells(power_domains, wcl_power_wells);
+       else if (DISPLAY_VER(display) >= 30)
                return set_power_wells(power_domains, xe3lpd_power_wells);
        else if (DISPLAY_VER(display) >= 20)
                return set_power_wells(power_domains, xe2lpd_power_wells);