arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must
be supplied on CLKOUT0. Previously, our bootloader configured this
clock, which is why the PRU Ethernet ports appeared to work, but the
change never made it into the device tree.

Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Fixes: 87adfd1ab03a ("arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes")
Link: https://lore.kernel.org/r/20250521053339.1751844-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index f63c101b7d61a13ca799d6af6007281522e18a67..129524eb5b91238c55b7c3cbe521e6c58f5b1ca8 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -322,6 +322,8 @@
 &icssg0_mdio {
        pinctrl-names = "default";
        pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
+       assigned-clocks = <&k3_clks 157 123>;
+       assigned-clock-parents = <&k3_clks 157 125>;
        status = "okay";
 
        icssg0_phy1: ethernet-phy@1 {