/* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       E1000_WRITE_FLUSH();
        msleep(10);
 
        /* Test each interrupt */
                        adapter->test_icr = 0;
                        ew32(IMC, mask);
                        ew32(ICS, mask);
+                       E1000_WRITE_FLUSH();
                        msleep(10);
 
                        if (adapter->test_icr & mask) {
                adapter->test_icr = 0;
                ew32(IMS, mask);
                ew32(ICS, mask);
+               E1000_WRITE_FLUSH();
                msleep(10);
 
                if (!(adapter->test_icr & mask)) {
                        adapter->test_icr = 0;
                        ew32(IMC, ~mask & 0x00007FFF);
                        ew32(ICS, ~mask & 0x00007FFF);
+                       E1000_WRITE_FLUSH();
                        msleep(10);
 
                        if (adapter->test_icr) {
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       E1000_WRITE_FLUSH();
        msleep(10);
 
        /* Unhook test interrupt handler */
                        if (unlikely(++k == txdr->count)) k = 0;
                }
                ew32(TDT, k);
+               E1000_WRITE_FLUSH();
                msleep(200);
                time = jiffies; /* set the start time for the receive */
                good_cnt = 0;
 
        /* Must reset the PHY before resetting the MAC */
        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
                ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
+               E1000_WRITE_FLUSH();
                msleep(5);
        }
 
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
                udelay(1);
        }
 
                eecd &= ~E1000_EECD_SK; /* Lower SCK */
 
                ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
 
                udelay(hw->eeprom.delay_usec);
        } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | data;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
 
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       e1e_flush();
        usleep_range(10000, 20000);
 
        /* Test each interrupt */
                        adapter->test_icr = 0;
                        ew32(IMC, mask);
                        ew32(ICS, mask);
+                       e1e_flush();
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr & mask) {
                adapter->test_icr = 0;
                ew32(IMS, mask);
                ew32(ICS, mask);
+               e1e_flush();
                usleep_range(10000, 20000);
 
                if (!(adapter->test_icr & mask)) {
                        adapter->test_icr = 0;
                        ew32(IMC, ~mask & 0x00007FFF);
                        ew32(ICS, ~mask & 0x00007FFF);
+                       e1e_flush();
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr) {
 
        /* Disable all the interrupts */
        ew32(IMC, 0xFFFFFFFF);
+       e1e_flush();
        usleep_range(10000, 20000);
 
        /* Unhook test interrupt handler */
                             E1000_CTRL_FD);     /* Force Duplex to FULL */
 
                ew32(CTRL, ctrl_reg);
+               e1e_flush();
                udelay(500);
 
                return 0;
         */
 #define E1000_SERDES_LB_ON 0x410
        ew32(SCTL, E1000_SERDES_LB_ON);
+       e1e_flush();
        usleep_range(10000, 20000);
 
        return 0;
                    hw->phy.media_type == e1000_media_type_internal_serdes) {
 #define E1000_SERDES_LB_OFF 0x400
                        ew32(SCTL, E1000_SERDES_LB_OFF);
+                       e1e_flush();
                        usleep_range(10000, 20000);
                        break;
                }
                                k = 0;
                }
                ew32(TDT, k);
+               e1e_flush();
                msleep(200);
                time = jiffies; /* set the start time for the receive */
                good_cnt = 0;
 
        ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
        ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
        ew32(CTRL, ctrl);
+       e1e_flush();
        udelay(10);
        ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
        ew32(CTRL, ctrl);
        ew32(CTRL, reg);
 
        ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+       e1e_flush();
        udelay(20);
        ew32(CTRL, ctrl_reg);
        ew32(CTRL_EXT, ctrl_ext);
+       e1e_flush();
        udelay(20);
 
 out:
        ret_val = e1000_acquire_swflag_ich8lan(hw);
        e_dbg("Issuing a global reset to ich8lan\n");
        ew32(CTRL, (ctrl | E1000_CTRL_RST));
+       /* cannot issue a flush here because it hangs the hardware */
        msleep(20);
 
        if (!ret_val)
 
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                ew32(EECD, eecd);
+               e1e_flush();
                udelay(1);
 
                /*
 
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
        kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
                       E1000_KMRNCTRLSTA_OFFSET) | data;
        ew32(KMRNCTRLSTA, kmrnctrlsta);
+       e1e_flush();
 
        udelay(2);
 
 
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                wr32(E1000_EECD, eecd);
+               wrfl();
                udelay(1);
                timeout = NVM_MAX_RETRY_SPI;
 
 
 
        /* Disable all the interrupts */
        wr32(E1000_IMC, ~0);
+       wrfl();
        msleep(10);
 
        /* Define all writable bits for ICS */
 
                        wr32(E1000_IMC, mask);
                        wr32(E1000_ICS, mask);
+                       wrfl();
                        msleep(10);
 
                        if (adapter->test_icr & mask) {
 
                wr32(E1000_IMS, mask);
                wr32(E1000_ICS, mask);
+               wrfl();
                msleep(10);
 
                if (!(adapter->test_icr & mask)) {
 
                        wr32(E1000_IMC, ~mask);
                        wr32(E1000_ICS, ~mask);
+                       wrfl();
                        msleep(10);
 
                        if (adapter->test_icr & mask) {
 
        /* Disable all the interrupts */
        wr32(E1000_IMC, ~0);
+       wrfl();
        msleep(10);
 
        /* Unhook test interrupt handler */
 
                kfree(adapter->vf_data);
                adapter->vf_data = NULL;
                wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
+               wrfl();
                msleep(100);
                dev_info(&adapter->pdev->dev, "IOV Disabled\n");
        }
                kfree(adapter->vf_data);
                adapter->vf_data = NULL;
                wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
+               wrfl();
                msleep(100);
                dev_info(&pdev->dev, "IOV Disabled\n");
        }
 
        /* disable transmits */
        txdctl = er32(TXDCTL(0));
        ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
+       e1e_flush();
        msleep(10);
 
        /* Setup the HW Tx Head and Tail descriptor pointers */
        /* disable receives */
        rxdctl = er32(RXDCTL(0));
        ew32(RXDCTL(0), rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
+       e1e_flush();
        msleep(10);
 
        rdlen = rx_ring->count * sizeof(union e1000_adv_rx_desc);
 
         */
        *eecd_reg = *eecd_reg | IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
         */
        *eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, *eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
                        eecd_reg |= IXGB_EECD_DI;
 
                IXGB_WRITE_REG(hw, EECD, eecd_reg);
+               IXGB_WRITE_FLUSH(hw);
 
                udelay(50);
 
        /*  Deselect EEPROM  */
        eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Clock high  */
        eecd_reg |= IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Select EEPROM  */
        eecd_reg |= IXGB_EECD_CS;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Clock low  */
        eecd_reg &= ~IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
        /*  Rising edge of clock  */
        eecd_reg |= IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 
        /*  Falling edge of clock  */
        eecd_reg &= ~IXGB_EECD_SK;
        IXGB_WRITE_REG(hw, EECD, eecd_reg);
+       IXGB_WRITE_FLUSH(hw);
        udelay(50);
 }
 
 
         */
        IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
        IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
+       IXGB_WRITE_FLUSH(hw);
        msleep(IXGB_DELAY_BEFORE_RESET);
 
        /* Issue a global reset to the MAC.  This will reset the chip's
        ctrl &= ~IXGB_CTRL0_SDP2;
        ctrl |= IXGB_CTRL0_SDP3;
        IXGB_WRITE_REG(hw, CTRL0, ctrl);
+       IXGB_WRITE_FLUSH(hw);
 
        /* SerDes needs extra delay */
        msleep(IXGB_SUN_PHY_RESET_DELAY);
 
                autoc_reg |= IXGBE_AUTOC_AN_RESTART;
                autoc_reg |= IXGBE_AUTOC_FLU;
                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
+               IXGBE_WRITE_FLUSH(hw);
                usleep_range(10000, 20000);
        }
 
 
 
        /* Disable all the interrupts */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+       IXGBE_WRITE_FLUSH(&adapter->hw);
        usleep_range(10000, 20000);
 
        /* Test each interrupt */
                                        ~mask & 0x00007FFF);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                        ~mask & 0x00007FFF);
+                       IXGBE_WRITE_FLUSH(&adapter->hw);
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr & mask) {
                adapter->test_icr = 0;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
+               IXGBE_WRITE_FLUSH(&adapter->hw);
                usleep_range(10000, 20000);
 
                if (!(adapter->test_icr &mask)) {
                                        ~mask & 0x00007FFF);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                        ~mask & 0x00007FFF);
+                       IXGBE_WRITE_FLUSH(&adapter->hw);
                        usleep_range(10000, 20000);
 
                        if (adapter->test_icr) {
 
        /* Disable all the interrupts */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+       IXGBE_WRITE_FLUSH(&adapter->hw);
        usleep_range(10000, 20000);
 
        /* Unhook test interrupt handler */
 
        vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
        vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
        IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* take a breather then clean up driver data */
        msleep(100);
 
        *i2cctl |= IXGBE_I2C_CLK_OUT;
 
        IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* SCL rise time (1000ns) */
        udelay(IXGBE_I2C_T_RISE);
        *i2cctl &= ~IXGBE_I2C_CLK_OUT;
 
        IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* SCL fall time (300ns) */
        udelay(IXGBE_I2C_T_FALL);
                *i2cctl &= ~IXGBE_I2C_DATA_OUT;
 
        IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_FLUSH(hw);
 
        /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
        udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
 
        ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
        ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
        IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
+       IXGBE_WRITE_FLUSH(hw);
 
        msleep(50);