Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued

Backmerge the 4.8 pull request state from Dave - conflicts were
getting out of hand, and Chris has some patches which outright don't
apply without everything merged together again.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

diff --cc drivers/gpu/drm/i915/intel_csr.c
index 1ea0e1f433971ea201debcff43e36d6cd75a35f4,3edb9580928e5b30a35d855a87f6bcd66158b454..fb27d187876cedb845c08ac1bf9d75e40a697161
--- 1/drivers/gpu/drm/i915/intel_csr.c
--- 2/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@@ -32,9 -32,16 +32,9 @@@
   * onwards to drive newly added DMC (Display microcontroller) in display
   * engine to save and restore the state of display engine when it enter into
   * low-power state and comes back to normal.
 - *
 - * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
 - * FW_LOADED, FW_FAILED.
 - *
 - * Once the firmware is written into the registers status will be moved from
 - * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
 - * be moved to FW_FAILED.
   */
  
- #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
+ #define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
  MODULE_FIRMWARE(I915_CSR_KBL);
  #define KBL_CSR_VERSION_REQUIRED      CSR_VERSION(1, 1)
  

diff --cc drivers/gpu/drm/i915/intel_lrc.c
index 361977fd117016140942675a3238eff05c8427d3,414ddda4392255b1d5479c66b4d75f86235ea2e8..a07da548ff494029369699fdf771796177470200
--- 1/drivers/gpu/drm/i915/intel_lrc.c
--- 2/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@@ -925,9 -1094,10 +925,10 @@@ static int intel_logical_ring_workaroun
   * code duplication.
   */
  static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
 -                                              uint32_t *const batch,
 +                                              uint32_t *batch,
                                                uint32_t index)
  {
+       struct drm_i915_private *dev_priv = engine->i915;
        uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
  
        /*
@@@ -1090,16 -1282,9 +1092,16 @@@ static int gen9_init_indirectctx_bb(str
                return ret;
        index = ret;
  
 +      /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
 +      wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
 +      wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
 +      wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
 +                          GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
 +      wa_ctx_emit(batch, index, MI_NOOP);
 +
        /* WaClearSlmSpaceAtContextSwitch:kbl */
        /* Actual scratch location is at 128 bytes offset */
-       if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
+       if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
                uint32_t scratch_addr
                        = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
  

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge