drm/amdgpu: Fix Vega20 Perf counter for pcie_bw

The perf counter for Vega20 is 108, instead of 104 which it was on all
previous GPUs, so add a check to use the appropriate value.

Signed-off-by: Kent Russell <kent.russell@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 87152d8ef0df8735522272bb324c4b0ae2b607e4..5b8f5d9fc3c02b68e0915e012b2f43a2e191fce5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -717,9 +717,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
                return;
 
        /* Set the 2 events that we wish to watch, defined above */
-       /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+       /* Reg 40 is # received msgs */
        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
-       perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+       /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
+       if (adev->asic_type == CHIP_VEGA20)
+               perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
+                                       EVENT1_SEL, 108);
+       else
+               perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
+                                       EVENT1_SEL, 104);
 
        /* Write to enable desired perf counters */
        WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);