wifi: brcmfmac: Make read-only array cfg_offset static const

Don't populate the read-only array cfg_offset on the stack at run time,
instead make it static const.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Acked-by: Arend van Spriel <arend.vanspriel@broadcom.com>
Link: https://patch.msgid.link/20250619082554.1834654-1-colin.i.king@gmail.com
Signed-off-by: Johannes Berg <johannes.berg@intel.com>

diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
index 8f97562811d7fcb9d705611327452e217461104d..9747928a36509c8e15cff4508534489b1142d068 100644 (file)
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
@@ -654,17 +654,19 @@ brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 {
        struct brcmf_core *core;
-       u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
-                            BRCMF_PCIE_CFGREG_PM_CSR,
-                            BRCMF_PCIE_CFGREG_MSI_CAP,
-                            BRCMF_PCIE_CFGREG_MSI_ADDR_L,
-                            BRCMF_PCIE_CFGREG_MSI_ADDR_H,
-                            BRCMF_PCIE_CFGREG_MSI_DATA,
-                            BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
-                            BRCMF_PCIE_CFGREG_RBAR_CTRL,
-                            BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
-                            BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
-                            BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
+       static const u16 cfg_offset[] = {
+               BRCMF_PCIE_CFGREG_STATUS_CMD,
+               BRCMF_PCIE_CFGREG_PM_CSR,
+               BRCMF_PCIE_CFGREG_MSI_CAP,
+               BRCMF_PCIE_CFGREG_MSI_ADDR_L,
+               BRCMF_PCIE_CFGREG_MSI_ADDR_H,
+               BRCMF_PCIE_CFGREG_MSI_DATA,
+               BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
+               BRCMF_PCIE_CFGREG_RBAR_CTRL,
+               BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
+               BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
+               BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG
+       };
        u32 i;
        u32 val;
        u32 lsc;