drm/amdgpu: reserve more memory for MES runtime DRAM

This patch fixes a MES firmware boot failure issue
when backdoor loading the MES firmware.

MES firmware runtime DRAM size is changed to 512k,
the driver needs to reserve this amount of memory in
FB, otherwise adjacent memory will be overwritten by
the MES firmware startup code.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index b127ddf1c8078b5f9233f9056947410f3cd92a79..072c478665ade1a838f810bfadc10b32bf44a5eb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -58,6 +58,7 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
 
 #define MES_EOP_SIZE   2048
+#define GFX_MES_DRAM_SIZE      0x80000
 
 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
@@ -477,7 +478,13 @@ static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
                   le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
        fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 
-       r = amdgpu_bo_create_reserved(adev, fw_size,
+       if (fw_size > GFX_MES_DRAM_SIZE) {
+               dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
+                       pipe, fw_size, GFX_MES_DRAM_SIZE);
+               return -EINVAL;
+       }
+
+       r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
                                      64 * 1024,
                                      AMDGPU_GEM_DOMAIN_VRAM |
                                      AMDGPU_GEM_DOMAIN_GTT,
@@ -613,8 +620,8 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
        WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
                     upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 
-       /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
-       WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
+       /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
+       WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
 
        if (prime_icache) {
                /* invalidate ICACHE */