clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs

The default PLL2/3/4/6 multiplier and divider configurations are no
longer used after the conversion to fixed or variable fractional PLL
clock types.

Note that the default configurations are still documented in the
comments above the individual rcar_gen4_cpg_pll_config instances.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index e6e2c3c16c8d5befa7cdd701b37da30cab18d234..4c8e4c69c1bfaaa05c4c38da0e3b1bcc6aca7623 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -259,11 +259,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
                                         (((md) & BIT(13)) >> 13))
 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
-       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
-       { 1,            128,    1,      0,      0,      0,      0,      144,    1,      192,    1,      0,      0,      16,     },
-       { 1,            106,    1,      0,      0,      0,      0,      120,    1,      160,    1,      0,      0,      19,     },
-       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
-       { 2,            128,    1,      0,      0,      0,      0,      144,    1,      192,    1,      0,      0,      32,     },
+       /* EXTAL div    PLL1 mult/div   PLL5 mult/div   OSC prediv */
+       { 1,            128,    1,      192,    1,      16,     },
+       { 1,            106,    1,      160,    1,      19,     },
+       { 0,            0,      0,      0,      0,      0,      },
+       { 2,            128,    1,      192,    1,      32,     },
 };
 
 

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index b6b6012f7123862762971dfde6037721eee3c90b..f33342314b2ef99e03a583a0adbd31020b421a6c 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -188,11 +188,11 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
                                         (((md) & BIT(13)) >> 13))
 
 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
-       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
-       { 1,            200,    1,      150,    1,      200,    1,      0,      0,      200,    1,      134,    1,      15,     },
-       { 1,            160,    1,      120,    1,      160,    1,      0,      0,      160,    1,      106,    1,      19,     },
-       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
-       { 2,            160,    1,      120,    1,      160,    1,      0,      0,      160,    1,      106,    1,      38,     },
+       /* EXTAL div    PLL1 mult/div   PLL5 mult/div   OSC prediv */
+       { 1,            200,    1,      200,    1,      15,     },
+       { 1,            160,    1,      160,    1,      19,     },
+       { 0,            0,      0,      0,      0,      0,      },
+       { 2,            160,    1,      160,    1,      38,     },
 };
 
 static int __init r8a779f0_cpg_mssr_init(struct device *dev)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 901a86c6432298ed3a3e8b0148318c21e4ab2036..55c8dd032fc325c63727f21dc4d38b8e08ce0ca0 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -259,11 +259,11 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
                                         (((md) & BIT(13)) >> 13))
 
 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
-       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
-       { 1,            192,    1,      204,    1,      192,    1,      144,    1,      192,    1,      168,    1,      16,     },
-       { 1,            160,    1,      170,    1,      160,    1,      120,    1,      160,    1,      140,    1,      19,     },
-       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
-       { 2,            192,    1,      204,    1,      192,    1,      144,    1,      192,    1,      168,    1,      32,     },
+       /* EXTAL div    PLL1 mult/div   PLL5 mult/div   OSC prediv */
+       { 1,            192,    1,      192,    1,      16,     },
+       { 1,            160,    1,      160,    1,      19,     },
+       { 0,            0,      0,      0,      0,      0,      },
+       { 2,            192,    1,      192,    1,      32,     },
 };
 
 static int __init r8a779g0_cpg_mssr_init(struct device *dev)

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index c695891380ad107c84867fe3ea5df631727fc380..e03118bf42ac8a8671f8db43603a64b9ea44c134 100644 (file)
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -254,11 +254,11 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
                                         (((md) & BIT(13)) >> 13))
 
 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
-       /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
-       { 1,            192,    1,      240,    1,      192,    1,      240,    1,      192,    1,      168,    1,      16,     },
-       { 1,            160,    1,      200,    1,      160,    1,      200,    1,      160,    1,      140,    1,      19,     },
-       { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
-       { 2,            192,    1,      240,    1,      192,    1,      240,    1,      192,    1,      168,    1,      32,     },
+       /* EXTAL div    PLL1 mult/div   PLL5 mult/div   OSC prediv */
+       { 1,            192,    1,      192,    1,      16,     },
+       { 1,            160,    1,      160,    1,      19,     },
+       { 0,            0,      0,      0,      0,      0,      },
+       { 2,            192,    1,      192,    1,      32,     },
 };
 
 static int __init r8a779h0_cpg_mssr_init(struct device *dev)

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index fccc3090c7c34b70d3b4ea16f4bd390399371da6..717fd148464fed96735a9774f5f84f9262a07f78 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -65,16 +65,8 @@ struct rcar_gen4_cpg_pll_config {
        u8 extal_div;
        u8 pll1_mult;
        u8 pll1_div;
-       u8 pll2_mult;
-       u8 pll2_div;
-       u8 pll3_mult;
-       u8 pll3_div;
-       u8 pll4_mult;
-       u8 pll4_div;
        u8 pll5_mult;
        u8 pll5_div;
-       u8 pll6_mult;
-       u8 pll6_div;
        u8 osc_prediv;
 };