idpf: add support for SW triggered interrupts

SW triggered interrupts are guaranteed to fire after their timer
expires, unlike Tx and Rx interrupts which will only fire after the
timer expires _and_ a descriptor write back is available to be processed
by the driver.

Add the necessary fields, defines, and initializations to enable a SW
triggered interrupt in the vector's dyn_ctl register.

Reviewed-by: Madhu Chittim <madhu.chittim@intel.com>
Signed-off-by: Joshua Hay <joshua.a.hay@intel.com>
Tested-by: Krishneil Singh <krishneil.k.singh@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/idpf/idpf_dev.c b/drivers/net/ethernet/intel/idpf/idpf_dev.c
index 6c913a703df647eb6faef9c7890a4e7a90131db8..41e4bd49402a83660fc8fd29eb96431fb8a4cfed 100644 (file)
--- a/drivers/net/ethernet/intel/idpf/idpf_dev.c
+++ b/drivers/net/ethernet/intel/idpf/idpf_dev.c
@@ -101,6 +101,9 @@ static int idpf_intr_reg_init(struct idpf_vport *vport)
                intr->dyn_ctl_itridx_s = PF_GLINT_DYN_CTL_ITR_INDX_S;
                intr->dyn_ctl_intrvl_s = PF_GLINT_DYN_CTL_INTERVAL_S;
                intr->dyn_ctl_wb_on_itr_m = PF_GLINT_DYN_CTL_WB_ON_ITR_M;
+               intr->dyn_ctl_swint_trig_m = PF_GLINT_DYN_CTL_SWINT_TRIG_M;
+               intr->dyn_ctl_sw_itridx_ena_m =
+                       PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M;
 
                spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing,
                                               IDPF_PF_ITR_IDX_SPACING);

diff --git a/drivers/net/ethernet/intel/idpf/idpf_txrx.h b/drivers/net/ethernet/intel/idpf/idpf_txrx.h
index 9c1fe84108ed2e33870245a8888a2e9b26b06f4b..0f71a6f5557b9189670f4f4e2aa9dbc75506c06c 100644 (file)
--- a/drivers/net/ethernet/intel/idpf/idpf_txrx.h
+++ b/drivers/net/ethernet/intel/idpf/idpf_txrx.h
@@ -354,6 +354,8 @@ struct idpf_vec_regs {
  * @dyn_ctl_itridx_m: Mask for ITR index
  * @dyn_ctl_intrvl_s: Register bit offset for ITR interval
  * @dyn_ctl_wb_on_itr_m: Mask for WB on ITR feature
+ * @dyn_ctl_sw_itridx_ena_m: Mask for SW ITR index
+ * @dyn_ctl_swint_trig_m: Mask for dyn_ctl SW triggered interrupt enable
  * @rx_itr: RX ITR register
  * @tx_itr: TX ITR register
  * @icr_ena: Interrupt cause register offset
@@ -367,6 +369,8 @@ struct idpf_intr_reg {
        u32 dyn_ctl_itridx_m;
        u32 dyn_ctl_intrvl_s;
        u32 dyn_ctl_wb_on_itr_m;
+       u32 dyn_ctl_sw_itridx_ena_m;
+       u32 dyn_ctl_swint_trig_m;
        void __iomem *rx_itr;
        void __iomem *tx_itr;
        void __iomem *icr_ena;
@@ -437,7 +441,7 @@ struct idpf_q_vector {
        cpumask_var_t affinity_mask;
        __cacheline_group_end_aligned(cold);
 };
-libeth_cacheline_set_assert(struct idpf_q_vector, 112,
+libeth_cacheline_set_assert(struct idpf_q_vector, 120,
                            24 + sizeof(struct napi_struct) +
                            2 * sizeof(struct dim),
                            8 + sizeof(cpumask_var_t));
@@ -471,6 +475,8 @@ struct idpf_tx_queue_stats {
 #define IDPF_ITR_IS_DYNAMIC(itr_mode) (itr_mode)
 #define IDPF_ITR_TX_DEF                IDPF_ITR_20K
 #define IDPF_ITR_RX_DEF                IDPF_ITR_20K
+/* Index used for 'SW ITR' update in DYN_CTL register */
+#define IDPF_SW_ITR_UPDATE_IDX 2
 /* Index used for 'No ITR' update in DYN_CTL register */
 #define IDPF_NO_ITR_UPDATE_IDX 3
 #define IDPF_ITR_IDX_SPACING(spacing, dflt)    (spacing ? spacing : dflt)

diff --git a/drivers/net/ethernet/intel/idpf/idpf_vf_dev.c b/drivers/net/ethernet/intel/idpf/idpf_vf_dev.c
index aad62e270ae40ef43b6fc19ccfee8035ffb2469a..aba828abcb17187a4b32d4e59ddcbcaef2bb6003 100644 (file)
--- a/drivers/net/ethernet/intel/idpf/idpf_vf_dev.c
+++ b/drivers/net/ethernet/intel/idpf/idpf_vf_dev.c
@@ -101,6 +101,9 @@ static int idpf_vf_intr_reg_init(struct idpf_vport *vport)
                intr->dyn_ctl_itridx_s = VF_INT_DYN_CTLN_ITR_INDX_S;
                intr->dyn_ctl_intrvl_s = VF_INT_DYN_CTLN_INTERVAL_S;
                intr->dyn_ctl_wb_on_itr_m = VF_INT_DYN_CTLN_WB_ON_ITR_M;
+               intr->dyn_ctl_swint_trig_m = VF_INT_DYN_CTLN_SWINT_TRIG_M;
+               intr->dyn_ctl_sw_itridx_ena_m =
+                       VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_M;
 
                spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing,
                                               IDPF_VF_ITR_IDX_SPACING);