#7: - Miscellanous W7O specific stuff.
- W7O support for other boot ROMs.
- W7O failsafe boot mechanism (for VxWorks upgrades).
- W7O SPD support.
- W7O VPD support routines.
- Code cleanup.
#1: - allow generation of GNU stabs line number debugging symbols
for assembly sources ; this allows symbolic debugging of
assembly files.
- - fix probelms due to CYGWIN patches
+ - fix problems due to CYGWIN patches
#2: - Fix BEDBUG lossage when using GPR 0 in assembly mode.
- Allow BEDBUG to have a choice in whitespace between operand
delimiters.
#6: - Add digital temperature and thermostat support
- Add support for Dallas DS1621 and On Semi's LM75 DTTs.
- Add command to support the DTTs.
+ #7: - Miscellanous W7O specific stuff.
+ - W7O support for other boot ROMs.
+ - W7O failsafe boot mechanism (for VxWorks upgrades).
+ - W7O SPD support.
+ - W7O VPD support routines.
+ - Code cleanup.
* Add support for >2MB of flash memory on FADS boards
Patch by Laurent Pinchart, 05 Mar 2002
sbc8260 MPC8260
+Conn Clark <clark@esteem.com>
+
+ ESTEEM192E MPC8xx
+
+Frank Gottschling <fgottschling@eltec.de>
+
+ MHPC MPC8xx
+
+ BAB7xx MPC740/MPC750
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
ADS860 MPC8xx
- ESTEEM192E MPC8xx
FADS823 MPC8xx
FADS850SAR MPC8xx
FADS860T MPC8xx
IAD210 MPC8xx
MBX MPC8xx
MBX860T MPC8xx
- MHPC MPC8xx
NX823 MPC8xx
RPXClassic MPC8xx
RPXlite MPC8xx
EVB64260 MPC7xx_74xx
- BAB750 MPC750
-
#########################################################################
# End of MAINTAINERS list #
#########################################################################
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o fpga.o
+OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o watchdog.o
SOBJS = init.o post1.o
$(LIB): $(OBJS) $(SOBJS)
# Wave 7 Optics boards
#
-#TEXT_BASE = 0xFFFE0000
#TEXT_BASE = 0xFFF80000
-TEXT_BASE = 0xFFFD0000
+TEXT_BASE = 0xFFFC0000
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD)
+
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _ERROR_H_
-#define _ERROR_H_
-
-#define ERR_FF 0xff // fault during led test (2)
-#define ERR_00 0x00 // fault during led test (2)
-#define ERR_LED 0x01 // led test failed (1)(3)(4)
-#define ERR_RAMG 0x04 // fault during SDRAM data bus test (2)
-#define ERR_RAML 0x05 // SDRAM data bus fault in LSW chip (5)
-#define ERR_RAMH 0x06 // SDRAM data bus fault in MSW chip (6)
-#define ERR_RAMB 0x07 // SDRAM data bus fault both chips (5)(6)(7)
-#define ERR_ADDG 0x08 // fault during Address ghosting test (13)
-#define ERR_ADDL 0x09 //
-#define ERR_ADDH 0x0a //
-#define ERR_ADDB 0x0b // )
-#define ERR_R55G 0x0c // fault during SDRAM fill 55 test (2)
-#define ERR_R55L 0x0d // SDRAM fill test 55 failed in LSW chip (8)
-#define ERR_R55H 0x0e // SDRAM fill test 55 failed in MSW chip (9)
-#define ERR_R55B 0x0f // SDRAM fill test 55 failed in both chips (10)
-#define ERR_RAAG 0x10 // fault during SDRAM fill aa test (2)
-#define ERR_RAAL 0x11 // SDRAM fill test aa failed in LSW chip (8)
-#define ERR_RAAH 0x12 // SDRAM fill test aa failed in MSW chip (9)
-#define ERR_RAAB 0x13 // SDRAM fill test aa failed in both chips (10)
-#define ERR_R00G 0x14 // fault during SDRAM fill 00 test (2)
-#define ERR_R00L 0x15 // SDRAM fill test 00 failed in LSW chip (8)
-#define ERR_R00H 0x16 // SDRAM fill test 00 failed in MSW chip (9)
-#define ERR_R00B 0x17 // SDRAM fill test 00 failed in both chips (10)
-#define ERR_RTCG 0x18 // fault during RTC test
-#define ERR_RTCBAT 0x19 // RTC battery failure
-#define ERR_RTCVAL 0x20 // RTC not installed or broken
-#define ERR_FPGAG 0x21 // fault during FPGA programming
-#define ERR_XINIT0 0x22 // Xilinx - INIT line failed to go low
-#define ERR_XINIT1 0x23 // Xilinx - INIT line failed to go high
-#define ERR_XDONE1 0x24 // Xilinx - DONE line failed to go high
-#define ERR_XIMAGE 0x25 // Xilinx - Bad FPGA image in Flash
-#define ERR_POSTOK 0x55 // PANIC: psych... OK
-
-#if !defined(__ASSEMBLY__)
-extern void log_stat(int errcode);
-extern void log_warn(int errcode);
-extern void log_err(int errcode);
-#endif
-
-/*
-Debugging suggestions:
-(1) periferal data bus shorted or crossed
-(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
-(3) check p_we, p_r/w, p_oe, p_rdy lines.
-(4) check LED buffers
-(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
-(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
-(7) check SDRAM control lines and clocks
-(8) check decoupling caps, replace LSW SDRAM
-(9) check decoupling caps, replace MSW SDRAM
-(10)
-(11)
-(12)
-(13) SDRAM address shorted or unconnected, check sdram caps
-*/
-#endif /* _ERROR_H_ */
-
#include <ppc4xx.h>
#include <asm/processor.h>
+#include <watchdog.h>
+
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
unsigned long flash_init (void)
{
- unsigned long size_b0, size_b1;
int i;
+ unsigned long size_b0, base_b0;
+ unsigned long size_b1, base_b1;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
if (flash_info[1].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
+ size_b1, size_b1<<20);
return 0;
}
+ /* Calculate base addresses */
+ base_b0 = -size_b0;
+ base_b1 = -size_b1;
+
/* Setup offsets for Boot Flash */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+ flash_get_offsets (base_b0, &flash_info[0]);
- /* Monitor protection ON by default */
+ /* Protect board level data */
(void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1,
- &flash_info[0]);
+ base_b0,
+ flash_info[0].start[1] - 1,
+ &flash_info[0]);
+
+
+ /* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- flash_info[0].start[flash_info[0].sector_count - 1],
- flash_info[0].start[0] + flash_info[0].size - 1,
+ base_b0 + size_b0 - CFG_MONITOR_LEN,
+ base_b0 + size_b0 - 1,
&flash_info[0]);
- /* Protect the FPGA image by default */
+ /* Protect the FPGA image */
(void)flash_protect(FLAG_PROTECT_SET,
FLASH_BASE1_PRELIM,
FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN - 1,
&flash_info[1]);
+ /* Protect the default boot image */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN,
+ FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN + 0x600000 - 1,
+ &flash_info[1]);
+
/* Setup offsets for Main Flash */
flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[1]);
return (size_b0 + size_b1);
-}
-
-
+} /* end flash_init() */
/*-----------------------------------------------------------------------
*/
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}
-}
+} /* end flash_get_offsets() */
/*-----------------------------------------------------------------------
*/
}
switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("2 x AMD "); break;
- case FLASH_MAN_INTEL: printf ("1 x Intel "); break;
+ case FLASH_MAN_AMD: printf ("1 x AMD "); break;
+ case FLASH_MAN_STM: printf ("1 x STM "); break;
+ case FLASH_MAN_INTEL: printf ("2 x Intel "); break;
default: printf ("Unknown Vendor ");
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
- printf ("AM29LV040 (4096 Kbit, uniform sector size)\n");
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+ printf ("AM29LV040 (4096 Kbit, uniform sector size)\n");
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+ printf ("M29W040B (4096 Kbit, uniform block size)\n");
+ else
+ printf ("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n");
break;
case FLASH_28F320J3A:
printf ("28F320J3A (32 Mbit = 128K x 32)\n");
printf ("Unknown Chip Type\n");
}
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+ printf (" Size: %ld KB in %d Blocks\n",
+ info->size >> 10, info->sector_count);
+ } else {
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ }
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
);
}
printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
+} /* end flash_print_info() */
/*
* The following code cannot be run from FLASH!
case (unsigned char)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
+ case (unsigned char)STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
default:
*addr2 = 0xf0; /* no or unknown flash */
return 0;
value = *(addr2 + 1);
switch (value) {
case (unsigned char)AMD_ID_LV040B:
+ case (unsigned char)STM_ID_29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
}
return (info->size);
-}
+} /* end flash_get_size() */
-int wait_for_DQ7(flash_info_t *info, int sect)
+/*-----------------------------------------------------------------------
+ */
+
+static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout)
{
- ulong start, now, last;
- volatile unsigned char *addr = (unsigned char *)(info->start[sect]);
+ int i;
- start = get_timer (0);
- last = start;
- while ((addr[0] & (unsigned char)0x00800080) != (unsigned char)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
+ volatile uchar *vaddr = (uchar *)addr;
+
+ /* Loop X times */
+ for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */
+ udelay(10);
+ /* Pause 10 us */
+
+ /* Check for completion */
+ if ((vaddr[0] & 0x80) == (cmp_val & 0x80)) {
+ return 0;
}
+
+ /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */
+ if (!(i % 110000))
+ putc('.');
+
+ /* Kick the dog if needed */
+ WATCHDOG_RESET();
}
- return 0;
-}
+
+ return 1;
+} /* wait_for_DQ7() */
/*-----------------------------------------------------------------------
*/
-int flash_erase8(flash_info_t *info, int s_first, int s_last)
+static int flash_erase8(flash_info_t *info, int s_first, int s_last)
{
- volatile unsigned char *addr = (unsigned char *)(info->start[0]);
- volatile unsigned char *addr2;
+ int tcode, rcode = 0;
+ volatile uchar *addr = (uchar *)(info->start[0]);
+ volatile uchar *sector_addr;
int flag, prot, sect;
/* Validate arguments */
/* Check for protected sectors */
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
+ for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
prot++;
}
else
printf ("\n");
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr2 = (unsigned char *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2);
+ sector_addr = (uchar *)(info->start[sect]);
- *(addr + 0x555) = (unsigned char)0xAA;
- *(addr + 0x2aa) = (unsigned char)0x55;
- *(addr + 0x555) = (unsigned char)0x80;
- *(addr + 0x555) = (unsigned char)0xAA;
- *(addr + 0x2aa) = (unsigned char)0x55;
- *addr2 = (unsigned char)0x30; /* sector erase */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+ printf("Erasing block %p\n", sector_addr);
+ else
+ printf("Erasing sector %p\n", sector_addr);
+
+ /* Disable interrupts which might cause Flash to timeout */
+ flag = disable_interrupts();
+
+ *(addr + 0x555) = (uchar)0xAA;
+ *(addr + 0x2aa) = (uchar)0x55;
+ *(addr + 0x555) = (uchar)0x80;
+ *(addr + 0x555) = (uchar)0xAA;
+ *(addr + 0x2aa) = (uchar)0x55;
+ *sector_addr = (uchar)0x30; /* sector erase */
/*
* Wait for each sector to complete, it's more
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
+ * Takes up to 6 seconds.
*/
- wait_for_DQ7(info, sect);
+ tcode = wait_for_DQ7((ulong)sector_addr, 0x80, 6000);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* Make sure we didn't timeout */
+ if (tcode) {
+ printf ("Timeout\n");
+ rcode = 1;
+ }
}
}
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/* reset to read mode */
- addr = (unsigned char *)info->start[0];
- *addr = (unsigned char)0xF0; /* reset bank */
+ addr = (uchar *)info->start[0];
+ *addr = (uchar)0xF0; /* reset bank */
printf (" done\n");
- return 0;
-}
+ return rcode;
+} /* end flash_erase8() */
-int flash_erase32(flash_info_t *info, int s_first, int s_last)
+static int flash_erase32(flash_info_t *info, int s_first, int s_last)
{
int flag, sect;
ulong start, now, last;
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
+ WATCHDOG_RESET();
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
unsigned long status;
}
/* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
+ if ((now - last) > 990) { /* every second */
putc ('.');
last = now;
}
}
printf (" done\n");
return 0;
-}
+} /* end flash_erase32() */
-int flash_erase(flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
{
- if (info->start[0] == FLASH_BASE0_PRELIM)
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
return flash_erase8(info, s_first, s_last);
else
return flash_erase32(info, s_first, s_last);
-}
+} /* end flash_erase() */
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 1 - write timeout
* 2 - Flash not erased
*/
-int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+static int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
+ ulong start;
int i, l, rc;
+ start = get_timer (0);
+
wp = (addr & ~3); /* get lower word
aligned address */
}
wp += 4;
cnt -= 4;
+ if (get_timer(start) > 1000) { /* every second */
+ WATCHDOG_RESET();
+ putc ('.');
+ start = get_timer(0);
+ }
}
if (cnt == 0) {
}
return (write_word8(info, wp, data));
-}
+} /* end write_buff8() */
#define FLASH_WIDTH 4 /* flash bus width in bytes */
-int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+static int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
+ ulong start;
+
+ start = get_timer (0);
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
wp += FLASH_WIDTH;
cnt -= FLASH_WIDTH;
+ if (get_timer(start) > 990) { /* every second */
+ putc ('.');
+ start = get_timer(0);
+ }
}
if (cnt == 0) {
}
return (write_word32(info, wp, data));
-}
+} /* write_buff32() */
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
int retval;
- if (info->start[0] == FLASH_BASE0_PRELIM)
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
retval = write_buff8(info, src, addr, cnt);
else
retval = write_buff32(info, src, addr, cnt);
return retval;
-}
+} /* end write_buff() */
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
static int write_word8(flash_info_t *info, ulong dest, ulong data)
{
- volatile unsigned char *addr2 = (unsigned char *)(info->start[0]);
- volatile unsigned char *dest2 = (unsigned char *)dest;
- volatile unsigned char *data2 = (unsigned char *)&data;
- ulong start;
+ volatile uchar *addr2 = (uchar *)(info->start[0]);
+ volatile uchar *dest2 = (uchar *)dest;
+ volatile uchar *data2 = (uchar *)&data;
int flag;
- int i;
+ int i, tcode, rcode = 0;
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile unsigned char *)dest) &
- (unsigned char)data) != (unsigned char)data) {
+ /* Check if Flash is (sufficently) erased */
+ if ((*((volatile uchar *)dest) &
+ (uchar)data) != (uchar)data) {
return (2);
}
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
+
+ for (i=0; i < (4 / sizeof(uchar)); i++) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
- for (i=0; i<4/sizeof(unsigned char); i++)
- {
- *(addr2 + 0x555) = (unsigned char)0xAA;
- *(addr2 + 0x2aa) = (unsigned char)0x55;
- *(addr2 + 0x555) = (unsigned char)0xA0;
+ *(addr2 + 0x555) = (uchar)0xAA;
+ *(addr2 + 0x2aa) = (uchar)0x55;
+ *(addr2 + 0x555) = (uchar)0xA0;
- dest2[i] = data2[i];
+ dest2[i] = data2[i];
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (unsigned char)0x80) !=
- (data2[i] & (unsigned char)0x80)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
+ /* Wait for write to complete, up to 1ms */
+ tcode = wait_for_DQ7((ulong)&dest2[i], data2[i], 1);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
- return (0);
-}
+ /* Make sure we didn't timeout */
+ if (tcode) {
+ rcode = 1;
+ }
+ }
+
+ return rcode;
+} /* end write_word8() */
static int write_word32(flash_info_t *info, ulong dest, ulong data)
{
start = get_timer (0);
while (((status = *addr) & 0x00800080) != 0x00800080) {
+ WATCHDOG_RESET();
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*addr = 0x00FF00FF; /* restore read mode */
return (1);
*addr = 0x00FF00FF; /* restore read mode */
return (0);
-}
+} /* end write_word32() */
static int _flash_protect(flash_info_t *info, long sector)
{
int i;
- ulong start;
- ulong status = 0;
+ int flag;
+ ulong status;
+ int rcode = 0;
volatile long *addr = (unsigned long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
case FLASH_28F640J3A:
case FLASH_28F128J3A:
- *addr = 0x00550055L; /* Clear the status register */
+ /* Disable interrupts which might cause Flash to timeout */
+ flag = disable_interrupts();
+
+ /* Issue command */
+ *addr = 0x00500050L; /* Clear the status register */
*addr = 0x00600060L; /* Set lock bit setup */
*addr = 0x00010001L; /* Set lock bit confirm */
/* Wait for command completion */
- start = get_timer (0);
- do {
- if (get_timer(start) > 1) { /* 75us time out, wait 1ms */
- printf("Protect %x sector TIMEOUT\n", (uint)sector);
- *addr = 0x00ff00ffL; /* restore read mode */
- return 1;
- }
- } while ((*addr & 0x00800080L) != 0x00800080L);
+ for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */
+ udelay(10);
+ if ((*addr & 0x00800080L) == 0x00800080L)
+ break;
+ }
/* Not successful? */
status = *addr;
- if ((status & ~0x00800080L) != 0x0L) {
+ if (status != 0x00800080L) {
printf("Protect %x sector failed: %x\n",
(uint)sector, (uint)status);
- *addr = 0x00ff00ffL;
- return 1;
+ rcode = 1;
}
- *addr = 0x00ff00ffL; /* restore read mode */
+
+ /* Restore read mode */
+ *addr = 0x00ff00ffL;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
break;
case FLASH_AM040: /* No soft sector protection */
break;
}
}
- return 0;
+ return rcode;
} /* end _flash_protect() */
static int _flash_unprotect(flash_info_t *info, long sector)
{
int i;
- ulong start;
- ulong status = 0;
+ int flag;
+ ulong status;
int rcode = 0;
volatile long *addr = (unsigned long *)sector;
case FLASH_28F320J3A:
case FLASH_28F640J3A:
case FLASH_28F128J3A:
- *addr = 0x00550055L; /* Clear the status register */
+ /* Disable interrupts which might cause Flash to timeout */
+ flag = disable_interrupts();
+
+ *addr = 0x00500050L; /* Clear the status register */
*addr = 0x00600060L; /* Clear lock bit setup */
*addr = 0x00D000D0L; /* Clear lock bit confirm */
/* Wait for command completion */
- start = get_timer (0);
- do {
+ for (i = 0; i < 80 ; i++) { /* 700ms timeout, wait 800 */
udelay(10000); /* Delay 10ms */
- if (get_timer(start) > 800) {/* 700ms time out, wait 800 */
- printf("Un-protect %x sector TIMEOUT\n", (uint)sector);
- *addr = 0x00ff00ffL; /* restore read mode */
- return 1;
- }
- } while ((*addr & 0x00800080L) != 0x00800080L);
-
+ if ((*addr & 0x00800080L) == 0x00800080L)
+ break;
+ }
/* Not successful? */
status = *addr;
- if ((status & ~0x00800080L) != 0x0L) {
+ if (status != 0x00800080L) {
printf("Un-protect %x sector failed: %x\n",
(uint)sector, (uint)status);
*addr = 0x00ff00ffL;
- return 1;
+ rcode = 1;
}
- *addr = 0x00ff00ffL; /* restore read mode */
+
+ /* restore read mode */
+ *addr = 0x00ff00ffL;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
break;
case FLASH_AM040: /* No soft sector protection */
break;
if (info->start[i] != sector) {
if (info->protect[i]) {
if (_flash_protect(info, info->start[i]))
- rcode = 1;
+ rcode = 1;
}
}
else /* Turn protection off for this sector */
int rcode;
if (prot)
- rcode = _flash_protect(info, sector);
+ rcode = _flash_protect(info, info->start[sector]);
else
- rcode = _flash_unprotect(info, sector);
+ rcode = _flash_unprotect(info, info->start[sector]);
return rcode;
-}
+} /* end flash_real_protect() */
/*-----------------------------------------------------------------------
*/
+
#include <ppcboot.h>
#include "w7o.h"
#include <asm/processor.h>
-#include "error.h"
+#include "errors.h"
-
-static void fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
+static void
+fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
{
unsigned long i;
volatile unsigned long val;
- volatile unsigned short *dest = daddr; /* volatile - bypass optimizer */
+ volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
for (i = 0; i < len; i++, src++) {
val = *src;
}
-int fpgaDownload(unsigned char *saddr,
- unsigned long size,
- unsigned short *daddr)
+int
+fpgaDownload(unsigned char *saddr,
+ unsigned long size,
+ unsigned short *daddr)
{
- int i; /* index, intr disable flag */
- int start; /* timer */
- unsigned long greg, grego; /* GPIO & output register */
- unsigned long length; /* image size in words */
- unsigned long *source; /* image source addr */
- unsigned short *dest; /* destination FPGA addr */
- volatile unsigned short *ndest; /* temp destination FPGA addr */
- volatile unsigned short val; /* temp val */
- unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
+ int i; /* index, intr disable flag */
+ int start; /* timer */
+ unsigned long greg, grego; /* GPIO & output register */
+ unsigned long length; /* image size in words */
+ unsigned long *source; /* image source addr */
+ unsigned short *dest; /* destination FPGA addr */
+ volatile unsigned short *ndest; /* temp dest FPGA addr */
+ volatile unsigned short val; /* temp val */
+ unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
unsigned long eirq = GPIO_XCV_IRQ;
- int retval = -1; /* Function return value */
+ int retval = -1; /* Function return value */
/* Setup some basic values */
- length = (size / 4) + 1; /* size in words, rounding UP
- is OK */
+ length = (size / 4) + 1; /* size in words, rounding UP
+ is OK */
source = (unsigned long *)saddr;
dest = (unsigned short *)daddr;
grego = in32(IBM405GP_GPIO0_OR);
/* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
+ grego &= ~GPIO_XCV_PROG; /* PROG line low */
out32(IBM405GP_GPIO0_OR, grego);
/* Setup timeout timer */
start = get_timer(0);
/* Wait for FPGA init line */
- while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait for INIT line low */
+ while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
/* Check for timeout - 100us max, so use 3ms */
if (get_timer(start) > 3) {
printf(" failed to start init.\n");
- log_warn(ERR_XINIT0); /* Don't halt */
+ log_warn(ERR_XINIT0); /* Don't halt */
/* Reset line stays low */
- goto done; /* I like gotos... */
+ goto done; /* I like gotos... */
}
}
/* Unreset FPGA */
- grego |= GPIO_XCV_PROG; /* PROG line high */
+ grego |= GPIO_XCV_PROG; /* PROG line high */
out32(IBM405GP_GPIO0_OR, grego);
/* Wait for FPGA end of init period . */
- while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT line hi */
+ while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
/* Check for timeout */
if (get_timer(start) > 3) {
log_warn(ERR_XINIT1);
/* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
+ grego &= ~GPIO_XCV_PROG; /* PROG line low */
out32(IBM405GP_GPIO0_OR, grego);
goto done;
ndest = dest;
for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
/* Toggle IRQ/GPIO */
- greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
- greg |= eirq; /* toggle irq/gpio */
- mtdcr(CPC0_CR0, greg); /* ... just do it */
+ greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
+ greg |= eirq; /* toggle irq/gpio */
+ mtdcr(CPC0_CR0, greg); /* ... just do it */
/* turn on open drain for CNFG */
- greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */
- greg |= cnfg; /* CNFG open drain */
- out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */
+ greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */
+ greg |= cnfg; /* CNFG open drain */
+ out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */
/* Turn output enable on for CNFG */
- greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
- greg |= cnfg; /* CNFG tristate inactive */
- out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
+ greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
+ greg |= cnfg; /* CNFG tristate inactive */
+ out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
/* Setup FPGA for programming */
- grego &= ~cnfg; /* CONFIG line low */
+ grego &= ~cnfg; /* CONFIG line low */
out32(IBM405GP_GPIO0_OR, grego);
/*
fpga_img_write(source, length, (unsigned short *)ndest);
/* Done programming */
- grego |= cnfg; /* CONFIG line high */
+ grego |= cnfg; /* CONFIG line high */
out32(IBM405GP_GPIO0_OR, grego);
/* Turn output enable OFF for CNFG */
- greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
- greg &= ~cnfg; /* CNFG tristate inactive */
- out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
+ greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
+ greg &= ~cnfg; /* CNFG tristate inactive */
+ out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
/* Toggle IRQ/GPIO */
- greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
- greg &= ~eirq; /* toggle irq/gpio */
- mtdcr(CPC0_CR0, greg); /* ... just do it */
+ greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
+ greg &= ~eirq; /* toggle irq/gpio */
+ mtdcr(CPC0_CR0, greg); /* ... just do it */
ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */
- cnfg >>= 1; /* XXX - Next */
+ cnfg >>= 1; /* XXX - Next */
eirq >>= 1;
}
start = get_timer(0);
/* Wait for FPGA end of programming period . */
- while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE line low */
+ while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
/* Check for timeout */
if (get_timer(start) > 3) {
log_warn(ERR_XDONE1);
/* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
+ grego &= ~GPIO_XCV_PROG; /* PROG line low */
out32(IBM405GP_GPIO0_OR, grego);
goto done;
}
}
- printf("\n FPGA load succeeded.\n");
- retval = 0; /* Program OK */
+ printf("\n FPGA load succeeded\n");
+ retval = 0; /* Program OK */
done:
-
return retval;
}
int init_fpga(void)
{
- unsigned int i,j,ptr; // these are general purpose
- unsigned char bufchar; // general purpose charactor
- unsigned char *buf; // start of image pointer
- unsigned long len; // length of image
- unsigned char *fn_buf; // start of file name string
- unsigned int fn_len; // length of file name string
- unsigned char *xcv_buf; // pointer to start of fpga bit file image
- unsigned long xcv_len; // length of fpga bit file image
- unsigned long crc; // 30bit crc stored in image
- unsigned long calc_crc; // 30bit crc calculated from image
+ unsigned int i,j,ptr; /* General purpose */
+ unsigned char bufchar; /* General purpose character */
+ unsigned char *buf; /* Start of image pointer */
+ unsigned long len; /* Length of image */
+ unsigned char *fn_buf; /* Start of filename string */
+ unsigned int fn_len; /* Length of filename string */
+ unsigned char *xcv_buf; /* Pointer to start of image */
+ unsigned long xcv_len; /* Length of image */
+ unsigned long crc; /* 30bit crc in image */
+ unsigned long calc_crc; /* Calc'd 30bit crc */
int retval = -1;
/* Tell the world what we are doing */
/*
* Get the stored image's CRC & length.
*/
- crc = *(unsigned long *)(buf+4); /* CRC is first long word */
- len = *(unsigned long *)(buf+8); /* Cimage len is next long word */
+ crc = *(unsigned long *)(buf+4); /* CRC is first long word */
+ len = *(unsigned long *)(buf+8); /* Image len is next long */
/* Pedantic */
if ((len < 0x133A4) || (len > 0x80000))
/*
* Get the file name pointer and length.
*/
-
- fn_len = (*(unsigned short *)(buf+12) & 0xff);/* filename length
- is next short */
+ fn_len = (*(unsigned short *)(buf+12) & 0xff); /* filename length
+ is next short */
fn_buf = buf + 14;
/*
* Get the FPGA image pointer and length length.
*/
-
- xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
- xcv_len = len - 14 - fn_len; /* fpga image length */
+ xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
+ xcv_len = len - 14 - fn_len; /* fpga image length */
/* Check for uninitialized FLASH */
if ((strncmp(buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
- goto bad_image;
+ goto bad_image;
/*
* Calculate and Check the image's CRC.
if (crc != calc_crc) {
printf("\nfailed - bad CRC\n");
goto done;
- }
+ }
- /* output the file name */
- printf("file name : ");
+ /* Output the file name */
+ printf("file name : ");
for (i=0;i<fn_len;i++) {
bufchar = fn_buf[+i];
if (bufchar<' ' || bufchar>'~') bufchar = '.';
/*
* find rest of display data
*/
- ptr = 15; // offset to ncd filename length in fpga image
- j= xcv_buf[ptr]; // get length of ncd filename
- if (j>32) goto bad_image;
- ptr=ptr+j+3; // skip ncd filename string + 3 bytes more bytes
+ ptr = 15; /* Offset to ncd filename
+ length in fpga image */
+ j = xcv_buf[ptr]; /* Get len of ncd filename */
+ if (j > 32) goto bad_image;
+ ptr = ptr + j + 3; /* skip ncd filename string +
+ 3 bytes more bytes */
+
/*
* output target device string
*/
- j= xcv_buf[ptr++]-1; // length of target string less terminator
- if (j>32) goto bad_image;
+ j = xcv_buf[ptr++] - 1; /* len of targ str less term */
+ if (j > 32) goto bad_image;
printf("\n target : ");
- for (i=0;i<j;i++){
- bufchar=(xcv_buf[ptr++]);
- if (bufchar<' ' || bufchar>'~') bufchar = '.';
- putc(bufchar);
+ for (i = 0; i < j; i++) {
+ bufchar = (xcv_buf[ptr++]);
+ if (bufchar<' ' || bufchar>'~') bufchar = '.';
+ putc(bufchar);
}
+
/*
* output compilation date string and time string
*/
- ptr+=3; // skip two bytes of unknown meaning
- printf("\n synth time : ");
- j=(xcv_buf[ptr++] - 1); // length of date string less terminator
- if (j>32) goto bad_image;
- for (i=0;i<j;i++){
- bufchar=(xcv_buf[ptr++]);
- if (bufchar<' ' || bufchar>'~') bufchar = '.';
- putc(bufchar);
+ ptr += 3; /* skip 2 bytes */
+ printf("\n synth time : ");
+ j = (xcv_buf[ptr++] - 1); /* len of date str less term */
+ if (j > 32) goto bad_image;
+ for (i = 0; i < j; i++) {
+ bufchar = (xcv_buf[ptr++]);
+ if (bufchar<' ' || bufchar>'~') bufchar = '.';
+ putc(bufchar);
}
- ptr+=3; // skip two bytes of unknown meaning
- printf(" - ");
- j=(xcv_buf[ptr++] - 1); // slen = targ dev string length
- if (j>32) goto bad_image;
- for (i=0;i<j;i++){
- bufchar=(xcv_buf[ptr++]);
- if (bufchar<' ' || bufchar>'~') bufchar = '.';
- putc(bufchar);
+
+ ptr += 3; /* Skip 2 bytes */
+ printf(" - ");
+ j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
+ if (j > 32) goto bad_image;
+ for (i = 0; i < j; i++) {
+ bufchar = (xcv_buf[ptr++]);
+ if (bufchar<' ' || bufchar>'~') bufchar = '.';
+ putc(bufchar);
}
- /*
+
+ /*
* output crc and length strings
*/
- printf("\n len & crc : 0x%lx 0x%lx",len,crc);
-
+ printf("\n len & crc : 0x%lx 0x%lx", len, crc);
- /*
+ /*
* Program the FPGA.
*/
retval = fpgaDownload((unsigned char*)xcv_buf, xcv_len,
return retval;
}
+void test_fpga(unsigned short *daddr)
+{
+ int i;
+ volatile unsigned short *ndest = daddr;
+
+ for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+#if defined(CONFIG_W7OLMG)
+ ndest[0x7e] = 0x55aa;
+ if (ndest[0x7e] != 0x55aa)
+ log_warn(ERR_XRW1 + i);
+ ndest[0x7e] = 0xaa55;
+ if (ndest[0x7e] != 0xaa55)
+ log_warn(ERR_XRW1 + i);
+ ndest[0x7e] = 0xc318;
+ if (ndest[0x7e] != 0xc318)
+ log_warn(ERR_XRW1 + i);
+
+#elif defined(CONFIG_W7OLMC)
+ ndest[0x800] = 0x55aa;
+ ndest[0x801] = 0xaa55;
+ ndest[0x802] = 0xc318;
+ ndest[0x4800] = 0x55aa;
+ ndest[0x4801] = 0xaa55;
+ ndest[0x4802] = 0xc318;
+ if ((ndest[0x800] != 0x55aa) ||
+ (ndest[0x801] != 0xaa55) ||
+ (ndest[0x802] != 0xc318))
+ log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
+ if ((ndest[0x4800] != 0x55aa) ||
+ (ndest[0x4801] != 0xaa55) ||
+ (ndest[0x4802] != 0xc318))
+ log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
+
+#else
+# error "Unknown W7O board configuration"
+#endif
+ }
+
+ printf(" FPGA ready\n");
+ return;
+}
+
-//------------------------------------------------------------------------------+
-//
-// This source code has been made available to you by IBM on an AS-IS
-// basis. Anyone receiving this source is licensed under IBM
-// copyrights to use it in any way he or she deems fit, including
-// copying it, modifying it, compiling it, and redistributing it either
-// with or without modifications. No license under IBM patents or
-// patent applications is to be implied by the copyright license.
-//
-// Any user of this software should understand that IBM cannot provide
-// technical support for this software and will not be responsible for
-// any consequences resulting from the use of this software.
-//
-// Any person who transfers this source code or any derivative work
-// must include the IBM copyright notice, this paragraph, and the
-// preceding two paragraphs in the transferred software.
-//
-// COPYRIGHT I B M CORPORATION 1995
-// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-//-------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Function: ext_bus_cntlr_init
-// Description: Initializes the External Bus Controller for the external
-// peripherals. IMPORTANT: For pass1 this code must run from
-// cache since you can not reliably change a peripheral banks
-// timing register (pbxap) while running code from that bank.
-// For ex., since we are running from ROM on bank 0, we can NOT
-// execute the code that modifies bank 0 timings from ROM, so
-// we run it from cache.
-// Bank 0 - Flash bank 0
-// Bank 1 - CAN0, CAN1, CAN2, CAN3
-// Bank 2 - Expansion Bus
-// Bank 3 - 16552
-// Bank 4 - FPGA internal (ADC, DAC, etc.)
-// Bank 5 - Flash bank 1 (dummy)
-//-----------------------------------------------------------------------------
+/******************************************************************************
+ *
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
+ *
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
#include <config.h>
#include <ppc4xx.h>
#include <asm/cache.h>
#include <asm/mmu.h>
- .globl tmp_stack_init
+/******************************************************************************
+ * Function: ext_bus_cntlr_init
+ *
+ * Description: Configures EBC Controller and a few basic chip selects.
+ *
+ * CS0 is setup to get the Boot Flash out of the addresss range
+ * so that we may setup a stack. CS7 is setup so that we can
+ * access and reset the hardware watchdog.
+ *
+ * IMPORTANT: For pass1 this code must run from
+ * cache since you can not reliably change a peripheral banks
+ * timing register (pbxap) while running code from that bank.
+ * For ex., since we are running from ROM on bank 0, we can NOT
+ * execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Notes: Does NOT use the stack.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
.globl ext_bus_cntlr_init
- .globl sdram_test
- .extern sramTest
-
-tmp_stack_init:
- // set up stack
- addis r1, 0, 0xfc00 // set stack (R1) to top of on chip memory
- // so we can use it as stack
- // set up 1st dummy frame to store stack under flow vector ( fake return addr)
- stwu r1, -8(r1) // Save back chain and move SP
- // set up 2nd dummy frame to store called function's return address
- addis r3, 0, 0xffff // set 1st link register to reset vector
- ori r3, r3, 0xfffc // so underflow resets everything
- stwu r1, -8(r1) // Save back chain and move SP
- stw r3, +12(r1) // Save link register (underflow vect)
- blr // return, were done
-
+ .type ext_bus_cntlr_init, @function
ext_bus_cntlr_init:
- mflr r4 // save link register
- bl ..getAddr
+ mflr r0
+ /********************************************************************
+ * Prefetch entire ext_bus_cntrl_init function into the icache.
+ * This is necessary because we are going to change the same CS we
+ * are executing from. Otherwise a CPU lockup may occur.
+ *******************************************************************/
+ bl ..getAddr
..getAddr:
- mflr r3 // get address of ..getAddr
- mtlr r4 // restore link register
- addi r4,0,14 // set ctr to 14; used to prefetch
- mtctr r4 // 14 cache lines to fit this function
- // in cache (gives us 8x10=80 instrctns)
-..ebcloop:
- icbt r0,r3 // prefetch cache line for addr in r3
- addi r3,r3,32 // move to next cache line
- bdnz ..ebcloop // continue for 10 cache lines
+ mflr r3 /* get address of ..getAddr */
- //-------------------------------------------------------------------
- // Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
+ /* Calculate number of cache lines for this function */
+ addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+ mtctr r4
+..ebcloop:
+ icbt r0, r3 /* prefetch cache line for addr in r3*/
+ addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+ bdnz ..ebcloop /* continue for $CTR cache lines */
+
+ /********************************************************************
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+ *******************************************************************/
+ addis r3, 0, 0x0
+ ori r3, r3, 0xA000 /* wait 200us from reset */
+ mtctr r3
..spinlp:
- bdnz ..spinlp // spin loop
-
- //-----------------------------------------------------------------------
- // Memory Bank 0 (Flash Bank 0) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x0305 // BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,
- ori r4,r4,0x0440 // TH=2,RE=0,SOR=0,BEM=1,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFE3 // BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 1 (Flash Bank 1) initialization (dummy for flash_init only!!!)
- //-----------------------------------------------------------------------
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x0385 // BME=0,TWT=7,CSN=1,OEN=1,WBN=0,WBF=0,
- ori r4,r4,0x0240 // TH=1,RE=0,SOR=0,BEM=1,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,0xF00F // BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),
- ori r4,r4,0xC000 // BW=0x10(32 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 2 RTC/NVRAM initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,0x0280 // BME=0,TWT=5,CSN=0,OEN=0,WBN=0,WBF=0,
- ori r4,r4,0x0240 // TH=1,RE=0,SOR=0,BEM=1,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,0xFC01 // BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 3 Core/Gateway FPGA 0
- //-----------------------------------------------------------------------
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
- addis r4,0,0x0200 // BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,
- ori r4,r4,0x0400 // TH=2,RE=0,SOR=0,BEM=0,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,0xFD01 // BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
-/// Core CS configuration
-#ifdef CONFIG_W7OLMC
- //-----------------------------------------------------------------------
- // Memory Bank 4 Core FPGA 1
- //-----------------------------------------------------------------------
- addi r4,0,pb4ap
- mtdcr ebccfga,r4
- addis r4,0,0x0200 // BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,
- ori r4,r4,0x0400 // TW=2,RE=0,SOR=0,BEM=0,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
- addis r4,0,0xFD11 // BAS=0xFD1,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 5 Core FPGA 2
- //-----------------------------------------------------------------------
- addi r4,0,pb5ap
- mtdcr ebccfga,r4
- addis r4,0,0x0200 // BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,
- ori r4,r4,0x0400 // TW=2,RE=0,SOR=0,BEM=0,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
- addis r4,0,0xFD21 // BAS=0xFD2,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 6 Core Not Used
- //-----------------------------------------------------------------------
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr ebccfgd,r4
-// Gateway Configuration
-#elif defined(CONFIG_W7OLMG)
- //-----------------------------------------------------------------------
- // SAM - Change PCIINT signal to PerWE
- //-----------------------------------------------------------------------
- mfdcr r4, 0xB2
- ori r4, r4, 0x4000
- mtdcr 0xB2, r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 4 SAM 8-bit
- //-----------------------------------------------------------------------
- addi r4,0,pb4ap
- mtdcr ebccfga,r4 // FIXME Comment
- addis r4,0,0x0284
- ori r4,r4,0x0380
- mtdcr ebccfgd,r4
-
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
- addis r4,0,0xFE87
- ori r4,r4,0x8000
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 5 SAM 16-bit
- //-----------------------------------------------------------------------
- addi r4,0,pb5ap
- mtdcr ebccfga,r4 // FIXME Comment
- addis r4,0,0x0284
- ori r4,r4,0x0380
- mtdcr ebccfgd,r4
-
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
- addis r4,0,0xFD87
- ori r4,r4,0xA000
- mtdcr ebccfgd,r4
- //-----------------------------------------------------------------------
- // Memory Bank 6 Not used -
- //-----------------------------------------------------------------------
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr ebccfgd,r4
-#else
-# error "Unknown W7O board configuration"
-#endif
-
- //-----------------------------------------------------------------------
- // Memory Bank 7 LEDs
- //-----------------------------------------------------------------------
- addi r4,0,pb7ap
- mtdcr ebccfga,r4
- addis r4,0,0x0305 // BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,
- ori r4,r4,0x0440 // TH=2,RE=0,SOR=0,BEM=1,PEN=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb7cr
- mtdcr ebccfga,r4
- addis r4,0,0xFE01 // BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xC000 // BW=0x2(32 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Setup OCM
- //-----------------------------------------------------------------------
- addis r4, 0, 0xf800 // OCM @ 0xf8000000
- mtdcr 0x1a, r4
- addis r4, 0, 0xC000 // OCM enabled
- mtdcr 0x1b, r4
-
-fugu:
- mflr r31 // Save SP
- bl tmp_stack_init // setup temporary stack
- bl kick_dog // Reset the watchdog
- mtlr r31 // Resort link register
- blr // Return to calling function
-
-//-----------------------------------------------------------------------------
-// Function: sdram_init
-// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
-//-----------------------------------------------------------------------------
- .globl sdram_init
-
+ bdnz ..spinlp /* spin loop */
+
+ /********************************************************************
+ * Setup External Bus Controller (EBC).
+ *******************************************************************/
+ addi r3, 0, epcr
+ mtdcr ebccfga, r3
+ addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
+ ori r4, r4, 0x0 /* Drive CS with external master */
+ mtdcr ebccfgd, r4
+
+ /********************************************************************
+ * Change PCIINT signal to PerWE
+ *******************************************************************/
+ mfdcr r4, cntrl1
+ ori r4, r4, 0x4000
+ mtdcr cntrl1, r4
+
+ /********************************************************************
+ * Memory Bank 0 (Flash Bank 0) initialization
+ *******************************************************************/
+ addi r3, 0, pb0ap
+ mtdcr ebccfga, r3
+ addis r4, 0, CFG_W7O_EBC_PB0AP@h
+ ori r4, r4, CFG_W7O_EBC_PB0AP@l
+ mtdcr ebccfgd, r4
+
+ addi r3, 0, pb0cr
+ mtdcr ebccfga, r3
+ addis r4, 0, CFG_W7O_EBC_PB0CR@h
+ ori r4, r4, CFG_W7O_EBC_PB0CR@l
+ mtdcr ebccfgd, r4
+
+#if defined(CFG_OCM_DATA_ADDR)
+ /********************************************************************
+ * Setup OCM - On Chip Memory, USED FOR INITIAL STACK.
+ *******************************************************************/
+ /* Setup OCM */
+ addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
+ mtdcr ocmdsarc, r3
+ addis r4, 0, 0xC000 /* OCM data area enabled */
+ mtdcr ocmdscntl, r4
+#endif /* OCM setup */
+
+ /********************************************************************
+ * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
+ *******************************************************************/
+ addi r3, 0, pb7ap
+ mtdcr ebccfga, r3
+ addis r4, 0, CFG_W7O_EBC_PB7AP@h
+ ori r4, r4, CFG_W7O_EBC_PB7AP@l
+ mtdcr ebccfgd, r4
+
+ addi r3, 0, pb7cr
+ mtdcr ebccfga, r3
+ addis r4, 0, CFG_W7O_EBC_PB7CR@h
+ ori r4, r4, CFG_W7O_EBC_PB7CR@l
+ mtdcr ebccfgd, r4
+
+ /* We are all done */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function: sdram_init
+ *
+ * Description: Configures SDRAM memory banks.
+ *
+ * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
+ * via the IIC bus and then configures the SDRAM memory
+ * banks appropriately. If Auto Memory Configuration is
+ * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
+ * SDRAM is soldered down.
+ *
+ * Notes: Expects that the stack is already setup.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl sdram_init
+ .type sdram_init, @function
sdram_init:
-
- mflr r31
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0008
- ori r4,r4,0x4001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- // To set the appropriate timings, we need to know the SDRAM speed.
- // We can use the PLB speed since the SDRAM speed is the same as
- // the PLB speed. The PLB speed is the FBK divider times the
- // 405GP reference clock, which on the Walnut board is 33Mhz.
- // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
- // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
- // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
- // maybe 133Mhz.
- //-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save link register */
+
+ /*
+ * First call spd_sdram to try to init SDRAM according to the
+ * contents of the SPD EEPROM. If the SPD EEPROM is blank or
+ * erronious, spd_sdram returns 0 in R3.
+ */
+ bl spd_sdram
+ addic. r3, r3, 0 /* Check for error, save dram size */
+ bne ..sdri_done /* If it worked, we're done... */
+
+ /********************************************************************
+ * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
+ * is the SMALLEST SDRAM size the 405 supports. We can do this
+ * because W7O boards have soldered on RAM, and there will always
+ * be some amount present. If we were using DIMMs, we should hang
+ * the board instead, since it doesn't have any RAM to continue
+ * running with.
+ *******************************************************************/
+
+ /*
+ * Disable memory controller to allow
+ * values to be changed.
+ */
+ addi r3, 0, mem_mcopt1
+ mtdcr memcfga, r3
+ addis r4, 0, 0x0
+ ori r4, r4, 0x0
+ mtdcr memcfgd, r4
+
+ /*
+ * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
+ * All other banks are disabled.
+ */
+ addi r3, 0, mem_mb0cf
+ mtdcr memcfga, r3
+ addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
+ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
+ mtdcr memcfgd, r4
+
+ /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
+ addi r4, 0, 0 /* Zero the data reg */
+
+ addi r3, r3, 4 /* Point to MB1CF reg */
+ mtdcr memcfga, r3 /* Set the address */
+ mtdcr memcfgd, r4 /* Zero the reg */
+
+ addi r3, r3, 4 /* Point to MB2CF reg */
+ mtdcr memcfga, r3 /* Set the address */
+ mtdcr memcfgd, r4 /* Zero the reg */
+
+ addi r3, r3, 4 /* Point to MB3CF reg */
+ mtdcr memcfga, r3 /* Set the address */
+ mtdcr memcfgd, r4 /* Zero the reg */
+
+ /********************************************************************
+ * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+ * To set the appropriate timings, we assume sdram is
+ * 100MHz (pc100 compliant).
+ *******************************************************************/
+
+ /*
+ * Set up SDTR1
+ */
+ addi r3, 0, mem_sdtr1
+ mtdcr memcfga, r3
+ addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
+ ori r4, r4, 0x400D
+ mtdcr memcfgd, r4
+
+ /*
+ * Set RTR
+ */
+ addi r3, 0, mem_rtr
+ mtdcr memcfga, r3
+ addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
+ mtdcr memcfgd, r4
+
+ /********************************************************************
+ * Delay to ensure 200usec have elapsed since reset. Assume worst
+ * case that the core is running 200Mhz:
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ *******************************************************************/
+ addis r3, 0, 0x0000
+ ori r3, r3, 0xA000 /* Wait 200us from reset */
+ mtctr r3
..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- bl kick_dog // Reset the watchdog
- bl test_led // test the LEDs
- bl test_sdram // test the dram
- mtlr r31
- blr
+ bdnz ..spinlp2 /* spin loop */
+
+ /********************************************************************
+ * Set memory controller options reg, MCOPT1.
+ *******************************************************************/
+ addi r3, 0, mem_mcopt1
+ mtdcr memcfga, r3
+ addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
+ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
+ mtdcr memcfgd, r4 /* EMDULR=1 */
+
+..sdri_done:
+ /* restore and return */
+ lwz r0, +12(r1) /* Get saved link register */
+ addi r1, r1, +8 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+.Lfe1: .size sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-//
-//Description:
-// Routine to exercise memory for the bringing up of our boards.
-//
+/*
+ * Description:
+ * Routine to exercise memory for the bringing up of our boards.
+ */
#include <config.h>
#include <ppc4xx.h>
#include <asm/cache.h>
#include <asm/mmu.h>
-#include "error.h"
+#include <watchdog.h>
+
+#include "errors.h"
#define _ASMLANGUAGE
.globl log_stat
.globl log_warn
.globl log_err
+ .globl temp_uart_init
+ .globl post_puts
+ .globl disp_hex
+
+/*****************************************************
+******* Text Strings for low level printing ******
+******* In section got2 *******
+*****************************************************/
+
+/*
+ * Define the text strings for errors and warnings.
+ * Switch to .data section.
+ */
+ .section ".data"
+err_str: .asciz "*** POST ERROR = "
+warn_str: .asciz "*** POST WARNING = "
+end_str: .asciz "\r\n"
+
+/*
+ * Enter the labels in Global Entry Table (GOT).
+ * Switch to .got2 section.
+ */
+ START_GOT
+ GOT_ENTRY(err_str)
+ GOT_ENTRY(warn_str)
+ GOT_ENTRY(end_str)
+ END_GOT
+
+/*
+ * Switch back to .text section.
+ */
+ .text
-//****************************************
-//****************************************
-//******** LED register test ********
-//****************************************
-//****************************************
+/****************************************
+ ****************************************
+ ******** LED register test ********
+ ****************************************
+ ***************************************/
test_led:
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -8(r1) // Save back chain and move SP
- stw r0, +12(r1) // Save link register
-
-#if defined(CONFIG_W7OLMG)
- addi r3, 0, ERR_FF // first test value is ffff
- addi r4, r3, 0 // save copy of pattern
- bl set_led // store first test value
- bl get_led // read it back
- xor. r4, r4, r3 // compare to original
- beq LED2 // next test
- addi r3, 0, ERR_LED // error code = 1
- bl log_err // display error and halt
-LED2: addi r3, 0, ERR_00 // 2nd test value is 0000
- addi r4, r3, 0 // save copy of pattern
- bl set_led // store first test value
- bl get_led // read it back
- xor. r4, r4, r3 // compare to original
- beq LED3 // next test
- addi r3, 0, ERR_LED // error code = 1
- bl log_err // display error and halt
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ addi r3, 0, ERR_FF /* first test value is ffff */
+ addi r4, r3, 0 /* save copy of pattern */
+ bl set_led /* store first test value */
+ bl get_led /* read it back */
+ xor. r4, r4, r3 /* compare to original */
+#if defined(CONFIG_W7OLMC)
+ andi. r4, r4, 0x00ff /* lmc has 8 bits */
+#else
+ andi. r4, r4, 0xffff /* lmg has 16 bits */
+#endif
+ beq LED2 /* next test */
+ addi r3, 0, ERR_LED /* error code = 1 */
+ bl log_err /* display error and halt */
+LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */
+ addi r4, r3, 0 /* save copy of pattern */
+ bl set_led /* store first test value */
+ bl get_led /* read it back */
+ xor. r4, r4, r3 /* compare to original */
+#if defined(CONFIG_W7OLMC)
+ andi. r4, r4, 0x00ff /* lmc has 8 bits */
+#else
+ andi. r4, r4, 0xffff /* lmg has 16 bits */
#endif
+ beq LED3 /* next test */
+ addi r3, 0, ERR_LED /* error code = 1 */
+ bl log_err /* display error and halt */
+
LED3: /* restore stack and return */
- lwz r0, +12(r1) // Get saved link register
- mtlr r0 // Restore link register
- addi r1, r1, +8 // Remove frame from stack
- blr // Return to calling function
-
-
-//****************************************
-//****************************************
-//******** SDRAM TESTS ********
-//****************************************
-//****************************************
-test_sdram:
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/****************************************
+ ****************************************
+ ******** SDRAM TESTS ********
+ ****************************************
+ ***************************************/
+test_sdram:
+ /* called with mem size in r3 */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stmw r30, +8(r1) /* save R30,R31 */
+ /* r30 is log2(mem size) */
+ /* r31 is mem size */
+
+ /* take log2 of total mem size */
+ addi r31, r3, 0 /* save total mem size */
+ addi r30, 0, 0 /* clear r30 */
+l2_loop:
+ srwi. r31, r31, 1 /* shift right 1 */
+ addi r30, r30, 1 /* count shifts */
+ bne l2_loop /* loop till done */
+ addi r30, r30, -1 /* correct for over count */
+ addi r31, r3, 0 /* save original size */
+
+ /* now kick the dog and test the mem */
+ WATCHDOG_RESET /* Reset the watchdog */
+ bl Data_Buster /* test crossed/shorted data lines */
+ addi r3, r30, 0 /* get log2(memsize) */
+ addi r4, r31, 0 /* get memsize */
+ bl Ghost_Buster /* test crossed/shorted addr lines */
+ addi r3, r31, 0 /* get mem size */
+ bl Bit_Buster /* check for bad internal bits */
+
+ /* restore stack and return */
+ lmw r30, +8(r1) /* Restore r30, r31 */
+ lwz r0, +20(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+
+/****************************************
+ ******** sdram data bus test ********
+ ***************************************/
+Data_Buster:
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -8(r1) // Save back chain and move SP
- stw r0, +12(r1) // Save link register
-
-//****************************************
-//******** sdram data bus test ********
-//****************************************
- // set up led register for this test
-Data_Buster:
- addi r3, 0, ERR_RAMG // set led code to 1
- bl log_stat // store test value
- //now test the dram data bus
- xor r7, r7, r7 // load r7 with 0
- xor r6, r6, r6 // load r6 with base address of sdram
- addis r5, 0, 0x5555 // load r4 with test value
- ori r5, r5, 0x5555
- stw r5,0(r6) // sto the value
- lwz r3,0(r6) // read it back
- xor r3,r3,r5 // compare it to original
- addis r5, 0, 0xaaaa // load r4 with test value
- ori r5, r5, 0xaaaa
- stw r5,0(r6) // sto the value
- lwz r4,0(r6) // read it back
- xor r4,r4,r5 // compare it to original
- or r3,r3,r4 // or together both error terms
- // now that we have the error bits, we have to decide which part they are in
- bl get_idx // r5 is now index to error
+ mflr r0 /* Get link register */
+ stwu r1, -24(r1) /* Save back chain and move SP */
+ stw r0, +28(r1) /* Save link register */
+ stmw r28, 8(r1) /* save r28 - r31 on stack */
+ /* r31 i/o register */
+ /* r30 sdram base address */
+ /* r29 5555 syndrom */
+ /* r28 aaaa syndrom */
+
+ /* set up led register for this test */
+ addi r3, 0, ERR_RAMG /* set led code to 1 */
+ bl log_stat /* store test value */
+ /* now test the dram data bus */
+ xor r30, r30, r30 /* load r30 with base addr of sdram */
+ addis r31, 0, 0x5555 /* load r31 with test value */
+ ori r31, r31, 0x5555
+ stw r31,0(r30) /* sto the value */
+ lwz r29,0(r30) /* read it back */
+ xor r29,r31,r29 /* compare it to original */
+ addis r31, 0, 0xaaaa /* load r31 with test value */
+ ori r31, r31, 0xaaaa
+ stw r31,0(r30) /* sto the value */
+ lwz r28,0(r30) /* read it back */
+ xor r28,r31,r28 /* compare it to original */
+ or r3,r28,r29 /* or together both error terms */
+ /*
+ * Now that we have the error bits,
+ * we have to decide which part they are in.
+ */
+ bl get_idx /* r5 is now index to error */
addi r3, r3, ERR_RAMG
- cmpwi r3, ERR_RAMG // check for errors
- beq db2 // skip if no errors
- bl log_err // log the error
-db2: b Ghost_Buster // on to next test
+ cmpwi r3, ERR_RAMG /* check for errors */
+ beq db_done /* skip if no errors */
+ bl log_err /* log the error */
+db_done:
+ lmw r28, 8(r1) /* restore r28 - r31 from stack */
+ lwz r0, +28(r1) /* Get saved link register */
+ addi r1, r1, +24 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
-//****************************************************
-//******** test for address ghosting in dram ********
-//****************************************************
+
+/****************************************************
+ ******** test for address ghosting in dram ********
+ ***************************************************/
Ghost_Buster:
- addi r3, 0, ERR_ADDG // set the leds for address ghost test
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -36(r1) /* Save back chain and move SP */
+ stw r0, +40(r1) /* Save link register */
+ stmw r25, 8(r1) /* save r25 - r31 on stack */
+ /* r31 = scratch register */
+ /* r30 is main referance loop counter,
+ 0 to 23 */
+ /* r29 is ghost loop count, 0 to 22 */
+ /* r28 is referance address */
+ /* r27 is ghost address */
+ /* r26 is log2 (mem size) =
+ number of byte addr bits */
+ /* r25 is mem size */
+
+ /* save the log2(mem size) and mem size */
+ addi r26, r3, 0 /* r26 is number of byte addr bits */
+ addi r25, r4, 0 /* r25 is mem size in bytes */
+
+ /* set the leds for address ghost test */
+ addi r3, 0, ERR_ADDG
bl set_led
- addi r7, 0, 0x00ff // r7 = one byte of set bits
- addi r8, 0, 0 // r8 = 0 for testing
- addi r9, 0, 1 // r9 = 1 this is shifted to get ghost addresses
- addi r6, 0, 0 // r6 is main referance loop counter, 0 to 23
- // r5 is ghost loop counter, 0 to 22
- // r4 is referance address
- // r3 is ghost address
-
- // first fill memory with zeros
- addis r4, 0, 0x0100 // cover 8M of longs
- mtctr r4 // setup base address
- addi r4, 0, 0 // r4 is address, start at 0
-0: stw r8, 0(r4) // Store zero value
- addi r4, r4, 4 // Increment to next word
- bdnz 0b // Round and round...
-
- // now do main test
+
+ /* first fill memory with zeros */
+ srwi r31, r25, 2 /* convert bytes to longs */
+ mtctr r31 /* setup byte counter */
+ addi r28, 0, 0 /* start at address at 0 */
+ addi r31, 0, 0 /* data value = 0 */
+clr_loop:
+ stw r31, 0(r28) /* Store zero value */
+ addi r28, r28, 4 /* Increment to next word */
+ andi. r27, r28, 0xffff /* check for 2^16 loops */
+ bne clr_skip /* if not there, then skip */
+ WATCHDOG_RESET /* kick the dog every now and then */
+clr_skip:
+ bdnz clr_loop /* Round and round... */
+
+ /* now do main test */
+ addi r30, 0, 0 /* start referance counter at 0 */
outside:
- // Calculate the referance address
- // the referance address is calculated by setting the (r6-1)bit of the base address
- // when r6=0, the referance address is the base address.
- // setting the bit is done with the following shift functions.
- slw r4,r9,r6 // tmp = 1 << i
- srwi r4,r4,1 // tmp = tmp >> 1
-
- // fill referance address with Fs
- stb r7,0(r4)
-
- // ghost (inner) loop, now check all posible ghosted addresses
- addi r5, 0, 0 // r5 is the ghosted loop counter,0 to 22
+ /*
+ * Calculate the referance address
+ * the referance address is calculated by setting the (r30-1)
+ * bit of the base address
+ * when r30=0, the referance address is the base address.
+ * thus the sequence 0,1,2,4,8,..,2^(n-1)
+ * setting the bit is done with the following shift functions.
+ */
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ addi r31, 0, 1 /* r31 = 1 */
+ slw r28, r31, r30 /* set bit coresponding to loop cnt */
+ srwi r28, r28, 1 /* then shift it right one so */
+ /* we start at location 0 */
+ /* fill referance address with Fs */
+ addi r31, 0, 0x00ff /* r31 = one byte of set bits */
+ stb r31,0(r28) /* save ff in referance address */
+
+ /* ghost (inner) loop, now check all posible ghosted addresses */
+ addi r29, 0, 0 /* start ghosted loop counter at 0 */
inside:
- // Calculate the ghost address
- // the ghost address is calculated by toggling the r6th bit of the referance address
- slw r3, r9, r5 // r3 = bit pattern, only r5th bit is set
- xor r3, r4, r3 // r3 = ghost address = ref addr with r5th bit flipped
-
- // now check for ghosting
- lbz r3,0(r3) // get contents
- cmpwi r3, 0 // compare read value to 0
- bne Casper // we found a ghost!
-
- // now close ghost ( inner ) loop
- addi r5, r5, 1 // increment inner loop counter
- cmpwi r5, 23 // check for last inner loop
- ble inside // do more inner loops
-
- // now close referance ( outer ) loop
- stb r8, 0(r4) // zero out the altered address loc.
- addi r6, r6, 1 // increment outer loop counter
- cmpwi r6, 24 // check for last inner loop
- ble outside // do more outer loops
-
- // were done, lets go home
- b Bit_Buster
-Casper: addi r3, 0, ERR_ADDG // get indexed error message
- b log_err // output led error code, halt everything
-
-//****************************************************
-//******** SDRAM data fill tests **********
-//****************************************************
+ /*
+ * Calculate the ghost address by flipping one
+ * bit of referance address. This gives the
+ * sequence 1,2,4,8,...,2^(n-1)
+ */
+ addi r31, 0, 1 /* r31 = 1 */
+ slw r27, r31, r29 /* set bit coresponding to loop cnt */
+ xor r27, r28, r27 /* ghost address = ref addr with
+ bit flipped*/
+
+ /* now check for ghosting */
+ lbz r31,0(r27) /* get content of ghost addr */
+ cmpwi r31, 0 /* compare read value to 0 */
+ bne Casper /* we found a ghost! */
+
+ /* now close ghost ( inner ) loop */
+ addi r29, r29, 1 /* increment inner loop counter */
+ cmpw r29, r26 /* check for last inner loop */
+ blt inside /* do more inner loops */
+
+ /* now close referance ( outer ) loop */
+ addi r31, 0, 0 /* r31 = zero */
+ stb r31, 0(28) /* zero out the altered address loc. */
+ /*
+ * Increment and check for end, count is zero based.
+ * With the ble, this gives us one more loops than
+ * address bits for sequence 0,1,2,4,8,...2^(n-1)
+ */
+ addi r30, r30, 1 /* increment outer loop counter */
+ cmpw r30, r26 /* check for last inner loop */
+ ble outside /* do more outer loops */
+
+ /* were done, lets go home */
+ b gb_done
+Casper: /* we found a ghost !! */
+ addi r3, 0, ERR_ADDF /* get indexed error message */
+ bl log_err /* log error led error code */
+gb_done: /* pack your bags, and go home */
+ lmw r25, 8(r1) /* restore r25 - r31 from stack */
+ lwz r0, +40(r1) /* Get saved link register */
+ addi r1, r1, +36 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+/****************************************************
+ ******** SDRAM data fill tests **********
+ ***************************************************/
Bit_Buster:
- addis r5, 0, 0x0400 // FIXME - hard coded @ 64MB 0x04000000
+ /* called with mem size in r3 */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+ stw r5, +12(r1) /* save r5 */
+
+ addis r5, r3, 0 /* save mem size */
- // Test 55555555
- addi r3, 0, ERR_R55G // set up error code in case we fail
- bl log_stat // store test value
+ /* Test 55555555 */
+ addi r3, 0, ERR_R55G /* set up error code in case we fail */
+ bl log_stat /* store test value */
addis r4, 0, 0x5555
ori r4, r4, 0x5555
bl fill_test
- // Test aaaaaaaa
- addi r3, 0, ERR_RAAG // set up error code in case we fail
- bl log_stat // store test value
+ /* Test aaaaaaaa */
+ addi r3, 0, ERR_RAAG /* set up error code in case we fail */
+ bl log_stat /* store test value */
addis r4, 0, 0xAAAA
ori r4, r4, 0xAAAA
bl fill_test
- // Test 00000000
- addi r3, 0, ERR_R00G // set up error code in case we fail
- bl log_stat // store test value
+ /* Test 00000000 */
+ addi r3, 0, ERR_R00G /* set up error code in case we fail */
+ bl log_stat /* store test value */
addis r4, 0, 0
ori r4, r4, 0
bl fill_test
-
-//****************************************************
-//******** finished these tests **********
-//****************************************************
/* restore stack and return */
- lwz r0, +12(r1) // Get saved link register
- mtlr r0 // Restore link register
- addi r1, r1, +8 // Remove frame from stack
- blr // Return to calling function
-
-
-
-//****************************************************
-//******** fill test ********
-//****************************************************
-// tests memory by filling with value, and reading back
-// r5 = Size of memory in bytes
-// r4 = Value to write
-// r3 = Error code
+ lwz r5, +12(r1) /* restore r4 */
+ lwz r4, +8(r1) /* restore r4 */
+ lwz r0, +20(r1) /* Get saved link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+
+/****************************************************
+ ******** fill test ********
+ ***************************************************/
+/* tests memory by filling with value, and reading back */
+/* r5 = Size of memory in bytes */
+/* r4 = Value to write */
+/* r3 = Error code */
fill_test:
- mflr r30
- bl kick_dog // Reset the watchdog
- // first fill memory with Value
- srawi r7, r5, 2 // convert bytes to longs
- mtctr r7 // setup counter
- addi r6, 0, 0 // Make r6 = addr 0
-0: stw r4, 0(r6) // Store value
- addi r6, r6, 4 // Increment to next word
- bdnz 0b // Round and round...
-
- bl kick_dog // Reset the watchdog
-
- // now confirm Value is in memory
- mtctr r7 // setup counter
- addi r6, 0, 0 // Make r6 = addr 0
-0: lwz r7, 0(r6) // get value from memory
- xor. r7, r7, r4 // Writen = Read ?
- bne ft_err // If bad, than halt
-2: addi r6, r6, 4 // Increment to next word
- bdnz 0b // Round and round...
-
- bl kick_dog // Reset the watchdog
- mtlr r30
- blr // return
-
-ft_err: addi r7, r3, 0 // save current led code
- addi r3, r7, 0 // get pattern in r3
- bl get_idx // get index from r3
- add r3, r3, r4 // add index to old led code
- bl log_err // output led error code, halt everything
-
-
-//****************************************************
-//******* get error index from r3 pattern ********
-//****************************************************
-get_idx: // r4 = (MSW(r3) !=0)*2 + (LSW(r3) !=0)
- andi. r4, r3, 0xffff // check for lower bits
- beq gi2 // skip if no bits set
- andis. r4, r3, 0xffff // check for upper bits
- beq gi3 // skip if no bits set
- addi r4, 0, 3 // both upper and lower bits set
- blr
-gi2: andis. r4, r3, 0xffff // check for upper bits
- beq gi4 // skip if no bits set
- addi r4, 0, 2 // only upper bits set
- blr
-gi3: addi r4, 0, 1 // only lower bits set
- blr
-gi4: addi r4, 0, 0 // no bits set
- blr
-
-//****************************************************
-//******** set LED to R5 and hang ********
-//****************************************************
-log_stat: // output a led code and continue
-set_led:
+ mflr r0 /* Get link register */
+ stwu r1, -32(r1) /* Save back chain and move SP */
+ stw r0, +36(r1) /* Save link register */
+ stmw r27, 8(r1) /* save r27 - r31 on stack */
+ /* r31 - scratch register */
+ /* r30 - memory address */
+ mr r27, r3
+ mr r28, r4
+ mr r29, r5
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ /* first fill memory with Value */
+ srawi r31, r29, 2 /* convert bytes to longs */
+ mtctr r31 /* setup counter */
+ addi r30, 0, 0 /* Make r30 = addr 0 */
+ft_0: stw r28, 0(r30) /* Store value */
+ addi r30, r30, 4 /* Increment to next word */
+ andi. r31, r30, 0xffff /* check for 2^16 loops */
+ bne ft_0a /* if not there, then skip */
+ WATCHDOG_RESET /* kick the dog every now and then */
+ft_0a: bdnz ft_0 /* Round and round... */
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ /* Now confirm Value is in memory */
+ srawi r31, r29, 2 /* convert bytes to longs */
+ mtctr r31 /* setup counter */
+ addi r30, 0, 0 /* Make r30 = addr 0 */
+ft_1: lwz r31, 0(r30) /* get value from memory */
+ xor. r31, r31, r28 /* Writen = Read ? */
+ bne ft_err /* If bad, than halt */
+ addi r30, r30, 4 /* Increment to next word */
+ andi. r31, r30, 0xffff /* check for 2^16 loops*/
+ bne ft_1a /* if not there, then skip */
+ WATCHDOG_RESET /* kick the dog every now and then */
+ft_1a: bdnz ft_1 /* Round and round... */
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ b fill_done /* restore and return */
+
+ft_err: addi r29, r27, 0 /* save current led code */
+ addi r27, r31, 0 /* get pattern in r27 */
+ bl get_idx /* get index from r27 */
+ add r27, r27, r29 /* add index to old led code */
+ bl log_err /* output led err code, halt CPU */
+
+fill_done:
+ lmw r27, 8(r1) /* restore r27 - r31 from stack */
+ lwz r0, +36(r1) /* Get saved link register */
+ addi r1, r1, +32 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/****************************************************
+ ******* get error index from r3 pattern ********
+ ***************************************************/
+get_idx: /* r3 = (MSW(r3) !=0)*2 +
+ (LSW(r3) !=0) */
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -12(r1) // Save back chain and move SP
- stw r0, +16(r1) // Save link register
- stw r4, +8(r1) // save R4
-
- addis r4, 0, 0xfe00 // LED buffer is at 0xfe000000
- xori r3,r3, 0xffff // complement led code since active low
- sth r3, 0(r4) // store first test value
- xori r3,r3, 0xffff // complement led code since active low
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ andi. r4, r3, 0xffff /* check for lower bits */
+ beq gi2 /* skip if no bits set */
+ andis. r4, r3, 0xffff /* check for upper bits */
+ beq gi3 /* skip if no bits set */
+ addi r3, 0, 3 /* both upper and lower bits set */
+ b gi_done
+gi2: andis. r4, r3, 0xffff /* check for upper bits*/
+ beq gi4 /* skip if no bits set */
+ addi r3, 0, 2 /* only upper bits set */
+ b gi_done
+gi3: addi r3, 0, 1 /* only lower bits set */
+ b gi_done
+gi4: addi r3, 0, 0 /* no bits set */
+gi_done:
+ /* restore stack and return */
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/****************************************************
+ ******** set LED to R5 and hang ********
+ ***************************************************/
+log_stat: /* output a led code and continue */
+set_led:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
+#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */
+ xori r3,r3, 0xffff /* complement led code, active low */
+ sth r3, 0(r4) /* store first test value */
+ xori r3,r3, 0xffff /* complement led code, active low */
+#else /* if not gateway, then don't invert */
+ sth r3, 0(r4) /* store first test value */
+#endif
/* restore stack and return */
- lwz r0, +16(r1) // Get saved link register
- mtlr r0 // Restore link register
- lwz r4, +8(r1) // restore r4
- addi r1, r1, +12 // Remove frame from stack
- blr // Return to calling function
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
get_led:
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -12(r1) // Save back chain and move SP
- stw r0, +16(r1) // Save link register
- stw r4, +8(r1) // save R4
-
- addis r4, 0, 0xfe00 // LED buffer is at 0xfe000000
- lhz r3, 0(r4) // store first test value
- xori r3,r3, 0xffff // complement led code since active low
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
+ lhz r3, 0(r4) /* store first test value */
+#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */
+ xori r3,r3, 0xffff /* complement led code, active low */
+#endif
/* restore stack and return */
- lwz r0, +16(r1) // Get saved link register
- mtlr r0 // Restore link register
- lwz r4, +8(r1) // restore r4
- addi r1, r1, +12 // Remove frame from stack
- blr // Return to calling function
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
-log_err: // output the error and hang the board ( for now )
+log_err: /* output the error and hang the board ( for now ) */
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -8(r1) // Save back chain and move SP
- stw r0, +12(r1) // Save link register
- bl set_led
-halt:
- b halt // hang
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r3, +8(r1) /* save a copy of error code */
+ bl set_led /* set the led pattern */
+ GET_GOT /* get GOT address in r14 */
+ lwz r3,GOT(err_str) /* get address of string */
+ bl post_puts /* output the warning string */
+ lwz r3, +8(r1) /* get error code */
+ addi r4, 0, 2 /* set disp length to 2 nibbles */
+ bl disp_hex /* output the error code */
+ lwz r3,GOT(end_str) /* get address of string */
+ bl post_puts /* output the warning string */
+halt:
+ b halt /* hang */
/* restore stack and return */
- lwz r0, +12(r1) // Get saved link register
- mtlr r0 // Restore link register
- addi r1, r1, +8 // Remove frame from stack
- blr // Return to calling function
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
-log_warn: // output a warning, then continue with operations
+log_warn: /* output a warning, then continue with operations */
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -8(r1) // Save back chain and move SP
- stw r0, +12(r1) // Save link register
-
- bl set_led // set the led pattern
- addis r3, 0, 0xf // r3 = 0xf4240 = 1e6
- ori r3, r3, 0x4240
- xor r4,r4,r4 // r4 = 0
- bl udelay // delay 1e6 usec = 1 sec
-
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stw r3, +8(r1) /* save a copy of error code */
+ stw r14, +12(r1) /* save a copy of r14 (used by GOT) */
+
+ bl set_led /* set the led pattern */
+ GET_GOT /* get GOT address in r14 */
+ lwz r3,GOT(warn_str) /* get address of string */
+ bl post_puts /* output the warning string */
+ lwz r3, +8(r1) /* get error code */
+ addi r4, 0, 2 /* set disp length to 2 nibbles */
+ bl disp_hex /* output the error code */
+ lwz r3,GOT(end_str) /* get address of string */
+ bl post_puts /* output the warning string */
+
+ addis r3, 0, 64 /* has a long delay */
+ mtctr r3
+log_2:
+ WATCHDOG_RESET /* this keeps dog from barking, */
+ /* and takes time */
+ bdnz log_2 /* loop till time expires */
+
/* restore stack and return */
- lwz r0, +12(r1) // Get saved link register
- mtlr r0 // Restore link register
- addi r1, r1, +8 // Remove frame from stack
- blr // Return to calling function
-
-//****************************************************
-//******** void kick_dog(void) ********
-//******** Toggle the watchdog line ********
-//****************************************************
- .section ".text"
- .globl kick_dog
- .align 2
- .type kick_dog, @function
-kick_dog:
+ lwz r0, +20(r1) /* Get saved link register */
+ lwz r14, +12(r1) /* restore r14 */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/*******************************************************************
+ * temp_uart_init
+ * Temporary UART initialization routine
+ * Sets up UART0 to run at 9600N81 off of the internal clock.
+ * R3-R4 are used.
+ ******************************************************************/
+temp_uart_init:
/* save the return info on stack */
- mflr r0 // Get link register
- stwu r1, -16(r1) // Save back chain and move SP
- stw r0, +20(r1) // Save link register
-
- /* Save r3/r4 since we might be called from asm */
- stw r4, +8(r1)
- stw r3, +12(r1)
-
- addis r4, 0, 0xfe00 // LED register is at 0xfe000000
-
- lhz r3, 0(r4) // Read register
- xori r3, r3, 0x8000 // Toggle watchdog bit
- sth r3, 0(r4)
+ mflr r0 /* Get link register */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save link register */
+
+ addis r3, 0, 0xef60
+ ori r3, r3, 0x0303 /* r3 = UART0_LCR */
+ addi r4, 0, 0x83 /* n81 format, divisor regs enabled */
+ stb r4, 0(r3)
+
+ /* set baud rate to use internal clock,
+ baud = (200e6/16)/31/42 = 9600 */
+
+ addis r3, 0, 0xef60 /* Address of baud divisor reg */
+ ori r3, r3, 0x0300 /* UART0_DLM */
+ addi r4, 0, +42 /* uart baud divisor LSB = 93 */
+ stb r4, 0(r3) /* baud = (200 /16)/14/93 */
+
+ addi r3, r3, 0x0001 /* uart baud divisor addr */
+ addi r4, 0, 0
+ stb r4, 0(r3) /* Divisor Latch MSB = 0 */
+
+ addis r3, 0, 0xef60
+ ori r3, r3, 0x0303 /* r3 = UART0_LCR */
+ addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */
+ stb r4, 0(r3)
+
+ /* output a few line feeds */
+ addi r3, 0, '\n' /* load line feed */
+ bl post_putc /* output the char */
+ addi r3, 0, '\n' /* load line feed */
+ bl post_putc /* output the char */
+
+ /* restore stack and return */
+ lwz r0, +12(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +8 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/**********************************************************************
+ ** post_putc
+ ** outputs charactor in R3
+ ** r3 returns the error code ( -1 if there is an error )
+ *********************************************************************/
+
+post_putc:
- /* Restore r3/r4 */
- lwz r3, +12(r1)
- lwz r4, +8(r1)
-
- /* restore stack and return */
- lwz r0, +20(r1) // Get saved link register
- mtlr r0 // Restore link register
- addi r1, r1, +16 // Remove frame from stack
- blr // Return to calling function
-// end kick_dog()
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -20(r1) /* Save back chain and move SP */
+ stw r0, +24(r1) /* Save link register */
+ stmw r29, 8(r1) /* save r29 - r31 on stack
+ r31 - uart base address
+ r30 - delay counter
+ r29 - scratch reg */
+
+ addis r31, 0, 0xef60 /* Point to uart base */
+ ori r31, r31, 0x0300
+ addis r30, 0, 152 /* Load about 10,000,000 ticks. */
+pputc_lp:
+ lbz r29, 5(r31) /* Read Line Status Register */
+ andi. r29, r29, 0x20 /* Check THRE status */
+ bne thre_set /* Branch if FIFO empty */
+ addic. r30, r30, -1 /* Decrement and check if empty. */
+ bne pputc_lp /* Try, try again */
+ addi r3, 0, -1 /* Load error code for timeout */
+ b pputc_done /* Bail out with error code set */
+thre_set:
+ stb r3, 0(r31) /* Store character to UART */
+ addi r3, 0, 0 /* clear error code */
+pputc_done:
+ lmw r29, 8(r1) /*restore r29 - r31 from stack */
+ lwz r0, +24(r1) /* Get saved link register */
+ addi r1, r1, +20 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/****************************************************************
+ post_puts
+ Accepts a null-terminated string pointed to by R3
+ Outputs to the serial port until 0x00 is found.
+ r3 returns the error code ( -1 if there is an error )
+*****************************************************************/
+post_puts:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r31, 8(r1) /* save r31 - char pointer */
+
+ addi r31, r3, 0 /* move pointer to R31 */
+pputs_nxt:
+ lbz r3, 0(r31) /* Get next character */
+ addic. r3, r3, 0 /* Check for zero */
+ beq pputs_term /* bail out if zero */
+ bl post_putc /* output the char */
+ addic. r3, r3, 0 /* check for error */
+ bne pputs_err
+ addi r31, r31, 1 /* point to next char */
+ b pputs_nxt /* loop till term */
+pputs_err:
+ addi r3, 0, -1 /* set error code */
+ b pputs_end /* were outa here */
+pputs_term:
+ addi r3, 0, 1 /* set success code */
+ /* restore stack and return */
+pputs_end:
+ lwz r31, 8(r1) /* restore r27 - r31 from stack */
+ lwz r0, +16(r1) /* Get saved link register */
+ addi r1, r1, +12 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+
+/********************************************************************
+ ***** disp_hex
+ ***** Routine to display a hex value from a register.
+ ***** R3 is value to display
+ ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word
+ ***** Returns -1 in R3 if there is an error ( ie serial port hangs )
+ ***** Returns 0 in R3 if no error
+ *******************************************************************/
+disp_hex:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stmw r30, 8(r1) /* save r30 - r31 on stack */
+ /* r31 output char */
+ /* r30 uart base address */
+ addi r30, 0, 8 /* Go through 8 nibbles. */
+ addi r31, r3, 0
+pputh_nxt:
+ rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */
+ andi. r3, r31, 0x0f /* Get nibble. */
+ addi r3, r3, 0x30 /* Add zero's ASCII code. */
+ cmpwi r3, 0x03a
+ blt pputh_out
+ addi r3, r3, 0x07 /* 0x27 for lower case. */
+pputh_out:
+ cmpw r30, r4
+ bgt pputh_skip
+ bl post_putc
+ addic. r3, r3, 0 /* check for error */
+ bne pputh_err
+pputh_skip:
+ addic. r30, r30, -1
+ bne pputh_nxt
+ xor r3, r3, r3 /* Clear error code */
+ b pputh_done
+pputh_err:
+ addi r3, 0, -1 /* set error code */
+pputh_done:
+ /* restore stack and return */
+ lmw r30, 8(r1) /* restore r30 - r31 from stack */
+ lwz r0, +20(r1) /* Get saved link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
#include <ppcboot.h>
#include "w7o.h"
#include <asm/processor.h>
-#include "error.h"
+#include "vpd.h"
+#include "errors.h"
+#include <watchdog.h>
-/* ------------------------------------------------------------------------- */
+unsigned long get_dram_size(void);
+
+/*
+ * Macros to transform values
+ * into environment strings.
+ */
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
-extern int init_fpga(void);
+/* ------------------------------------------------------------------------- */
int board_pre_init (void)
{
#if defined(CONFIG_W7OLMG)
- /*
- * Setup GPIO pins - reset devices.
- */
- out32(IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
- out32(IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
- out32(IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
- */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ /*
+ * Setup GPIO pins - reset devices.
+ */
+ out32(IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
+ out32(IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
+ out32(IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,
+ INT0 highest priority*/
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
#elif defined(CONFIG_W7OLMC)
- /*
- * Setup GPIO pins
- */
- out32(IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
- out32(IBM405GP_GPIO0_OR, 0x01800000); /* set output pins to default */
- out32(IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
- */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ /*
+ * Setup GPIO pins
+ */
+ out32(IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
+ out32(IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
+ out32(IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,
+ INT0 highest priority*/
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
#else /* Unknown */
-# error "Unknown W7O board configuration"
+# error "Unknown W7O board configuration"
#endif
- return 0;
+ WATCHDOG_RESET(); /* Reset the watchdog */
+ temp_uart_init(); /* init the uart for debug */
+ WATCHDOG_RESET(); /* Reset the watchdog */
+ test_led(); /* test the LEDs */
+ test_sdram(get_dram_size()); /* test the dram */
+ log_stat(ERR_POST1); /* log status,post1 complete */
+ return 0;
}
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
-#if 0
- int i;
- int index;
- int len;
-#endif
-
- if (!s || strncmp(s, "LMC", 3) || strncmp(s, "LMG", 3))
- {
- printf ("### No HW ID - assuming NOTHING\n");
- }
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
-#if 0
- printf("\n FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++)
- {
- len = fpgadata[index];
- printf("%s ", &(fpgadata[index+1]));
- index += len+3;
- }
-
- putc ('\n');
-#endif
- return (0);
+ VPD vpd;
+
+ /* VPD data present in I2C EEPROM */
+ if (vpd_get_data(CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
+ /*
+ * Known board type.
+ */
+ if (vpd.productId[0] &&
+ ((strncmp(vpd.productId, "GMM", 3) == 0) ||
+ (strncmp(vpd.productId, "CMM", 3) == 0))) {
+
+ /* Output board information on startup */
+ printf("\"%s\", revision '%c', serial# %ld, manufacturer %u\n",
+ vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
+ return (0);
+ }
+ }
+
+ printf ("### Unknown HW ID - assuming NOTHING\n");
+ return (1);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- return (64 * 1024*1024);
+ return get_dram_size();
}
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
+unsigned long get_dram_size (void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 64 MB - ok\n");
+ int tmp, i, regs[4];
+ int size = 0;
- return (0);
-}
+ /* Get bank Size registers */
+ mtdcr(memcfga, mem_mb0cf); /* get bank 0 config reg */
+ regs[0] = mfdcr(memcfgd);
-/* ------------------------------------------------------------------------- */
+ mtdcr(memcfga, mem_mb1cf); /* get bank 1 config reg */
+ regs[1] = mfdcr(memcfgd);
+
+ mtdcr(memcfga, mem_mb2cf); /* get bank 2 config reg */
+ regs[2] = mfdcr(memcfgd);
+
+ mtdcr(memcfga, mem_mb3cf); /* get bank 3 config reg */
+ regs[3] = mfdcr(memcfgd);
+
+ /* compute the size, add each bank if enabled */
+ for(i = 0; i < 4; i++) {
+ if (regs[i] & 0x0001) { /* if enabled, */
+ tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
+ tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
+ size += tmp;
+ }
+ }
+
+ return size;
+}
int
misc_init_f(void)
return 0;
}
+static void
+w7o_env_init(VPD *vpd)
+{
+ /*
+ * Read VPD
+ */
+ if (vpd_get_data(CFG_DEF_EEPROM_ADDR, vpd) != 0)
+ return;
+
+ /*
+ * Known board type.
+ */
+ if (vpd->productId[0] &&
+ ((strncmp(vpd->productId, "GMM", 3) == 0) ||
+ (strncmp(vpd->productId, "CMM", 3) == 0))) {
+ char buf[30];
+ char *eth;
+ unsigned char *serial = getenv("serial#");
+ unsigned char *ethaddr = getenv("ethaddr");
+
+ /* Set 'serial#' envvar if serial# isn't set */
+ if (!serial) {
+ sprintf(buf, "%s-%ld", vpd->productId, vpd->serialNum);
+ setenv("serial#", buf);
+ }
+
+ /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
+ eth = vpd->ethAddrs[0];
+ if (ethaddr && (strcmp(ethaddr, MK_STR(CONFIG_ETHADDR)) == 0)) {
+ /* Now setup ethaddr */
+ sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ eth[0], eth[1], eth[2], eth[3], eth[4], eth[5]);
+ setenv("ethaddr", buf);
+ }
+ }
+} /* w7o_env_init() */
+
+
void
misc_init_r(bd_t *bd)
{
+ VPD vpd; /* VPD information */
+
#if defined(CONFIG_W7OLMG)
- unsigned long greg; /* GPIO Register */
+ unsigned long greg; /* GPIO Register */
greg = in32(IBM405GP_GPIO0_OR);
+ /*
+ * XXX - Unreset devices - this should be moved into VxWorks driver code
+ */
+ greg |= 0x41800000L; /* SAM, PHY, Galileo */
- /* XXX - Unreset devices - this should be moved into VxWorks driver code */
- greg |= 0x41800000L; /* SAM, PHY, Galileo */
-
- out32(IBM405GP_GPIO0_OR, greg); /* set output pins to default */
+ out32(IBM405GP_GPIO0_OR, greg); /* set output pins to default */
#endif /* CONFIG_W7OLMG */
- init_fpga();
+ /*
+ * Initialize W7O environment variables
+ */
+ w7o_env_init(&vpd);
+
+ /*
+ * Initialize the FPGA(s).
+ */
+ if (init_fpga() == 0)
+ test_fpga((unsigned short *)CONFIG_FPGAS_BASE);
- log_stat(ERR_POSTOK); /* Okley, dokley */
+ /* More POST testing. */
+ post2();
+
+ /* Done with hardware initialization and POST. */
+ log_stat(ERR_POSTOK);
+
+ /* Call silly, fail safe boot init routine */
+ init_fsboot();
return;
}
+
#include <config.h>
/* IBM 405GP PowerPC GPIO registers */
-#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */
-#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
+#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */
+#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
+#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
+#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
/* IBM 405GP DCRs */
-#define CPC0_CR0 0xb1 /* Chip control register 0 */
+#define CPC0_CR0 0xb1 /* Chip control register 0 */
/* LMG FPGA <=> CPU GPIO signals */
-#define LMG_XCV_INIT 0x10000000L
-#define LMG_XCV_PROG 0x04000000L
-#define LMG_XCV_DONE 0x00400000L
-#define LMG_XCV_CNFG_0 0x08000000L
-#define LMG_XCV_IRQ_0 0x0L
+#define LMG_XCV_INIT 0x10000000L
+#define LMG_XCV_PROG 0x04000000L
+#define LMG_XCV_DONE 0x00400000L
+#define LMG_XCV_CNFG_0 0x08000000L
+#define LMG_XCV_IRQ_0 0x0L
/* LMC FPGA <=> CPU GPIO signals */
-#define LMC_XCV_INIT 0x00800000L
-#define LMC_XCV_PROG 0x40000000L
-#define LMC_XCV_DONE 0x01000000L
-#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */
-#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */
-#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */
-#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */
-#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */
-#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */
+#define LMC_XCV_INIT 0x00800000L
+#define LMC_XCV_PROG 0x40000000L
+#define LMC_XCV_DONE 0x01000000L
+#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */
+#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */
+#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */
+#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */
+#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */
+#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */
/*
* Setup FPGA <=> GPIO mappings
*/
#if defined(CONFIG_W7OLMG)
-# define GPIO_XCV_INIT LMG_XCV_INIT
-# define GPIO_XCV_PROG LMG_XCV_PROG
-# define GPIO_XCV_DONE LMG_XCV_DONE
-# define GPIO_XCV_CNFG LMG_XCV_CNFG_0
-# define GPIO_XCV_IRQ LMG_XCV_IRQ_0
-# define GPIO_GPIO_1 0x40000000L
-# define GPIO_GPIO_6 0x02000000L
-# define GPIO_GPIO_7 0x01000000L
-# define GPIO_GPIO_8 0x00800000L
+# define GPIO_XCV_INIT LMG_XCV_INIT
+# define GPIO_XCV_PROG LMG_XCV_PROG
+# define GPIO_XCV_DONE LMG_XCV_DONE
+# define GPIO_XCV_CNFG LMG_XCV_CNFG_0
+# define GPIO_XCV_IRQ LMG_XCV_IRQ_0
+# define GPIO_GPIO_1 0x40000000L
+# define GPIO_GPIO_6 0x02000000L
+# define GPIO_GPIO_7 0x01000000L
+# define GPIO_GPIO_8 0x00800000L
#elif defined(CONFIG_W7OLMC)
-# define GPIO_XCV_INIT LMC_XCV_INIT
-# define GPIO_XCV_PROG LMC_XCV_PROG
-# define GPIO_XCV_DONE LMC_XCV_DONE
-# define GPIO_XCV_CNFG LMC_XCV_CNFG_0
-# define GPIO_XCV_IRQ LMC_XCV_IRQ_0
+# define GPIO_XCV_INIT LMC_XCV_INIT
+# define GPIO_XCV_PROG LMC_XCV_PROG
+# define GPIO_XCV_DONE LMC_XCV_DONE
+# define GPIO_XCV_CNFG LMC_XCV_CNFG_0
+# define GPIO_XCV_IRQ LMC_XCV_IRQ_0
#else
# error "Unknown W7O board configuration"
#endif
+/* Power On Self Tests */
+extern void post2(void);
+extern int test_led(void);
+extern int test_sdram(unsigned long size);
+extern void test_fpga(unsigned short *daddr);
+
+/* FGPA */
+extern int init_fpga(void);
+
+/* Misc */
+extern int temp_uart_init(void);
+extern void init_fsboot(void);
+
#endif /* _W7O_H_ */
#define CONFIG_LOADADDR F0080000
-#undef CONFIG_ETHADDR /* Default, overridden at boot */
+#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.1.2
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
- CFG_CMD_EEPROM | CFG_CMD_ELF)
+ CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_VPD | CFG_CMD_REGINFO)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
+#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
+
+#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
-#define CFG_HUSH_PARSER /* Hush parse for ppcboot */
+#undef CFG_HUSH_PARSER /* No hush parse for ppcboot */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 384000
+
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE {9600}
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+/*-----------------------------------------------------------------------
+ * Set up values for external bus controller
+ * used by cpu_init.c
+ *-----------------------------------------------------------------------
+ */
+ /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
+#undef CONFIG_USE_PERWE
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* bank 0 is boot flash */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB0AP 0x03050440
+/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_W7O_EBC_PB0CR 0xFFE38000
+
+/* bank 1 is main flash */
+/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB1AP 0x04850240
+/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
+#define CFG_EBC_PB1CR 0xF00FC000
+
+/* bank 2 is RTC/NVRAM */
+/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB2AP 0x03000440
+/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB2CR 0xFC018000
+
+/* bank 3 is FPGA 0 */
+/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
+#define CFG_EBC_PB3AP 0x02000400
+/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB3CR 0xFD01A000
+
+/* bank 4 is FPGA 1 */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CFG_EBC_PB4AP 0x02000400
+/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB4CR 0xFD11A000
+
+/* bank 5 is FPGA 2 */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CFG_EBC_PB5AP 0x02000400
+/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB5CR 0xFD21A000
+
+/* bank 6 is unused */
+/* pb6ap = 0 */
+#define CFG_EBC_PB6AP 0x00000000
+/* pb6cr = 0 */
+#define CFG_EBC_PB6CR 0x00000000
+
+/* bank 7 is LED register */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB7AP 0x03050440
+/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
+#define CFG_W7O_EBC_PB7CR 0xFE01C000
+
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFFD0000
+#define CFG_FLASH_BASE 0xFFFC0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
-
/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in RAM)
*/
-#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
#define CONFIG_LOADADDR F0080000
-#undef CONFIG_ETHADDR /* Default, overridden at boot */
+#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.1.2
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
- CFG_CMD_EEPROM | CFG_CMD_ELF)
+ CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_VPD | CFG_CMD_REGINFO | \
+ CFG_CMD_DTT)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
+#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
+
+#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
-#define CFG_HUSH_PARSER /* Hush parse for ppcboot */
+#undef CFG_HUSH_PARSER /* No hush parse for ppcboot */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 384000
+
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE {9600}
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+/*-----------------------------------------------------------------------
+ * Set up values for external bus controller
+ * used by cpu_init.c
+ *-----------------------------------------------------------------------
+ */
+ /* use PerWE instead of PCI_INT ( these functions share a pin ) */
+#define CONFIG_USE_PERWE 1
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* bank 0 is boot flash */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB0AP 0x03050440
+/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_W7O_EBC_PB0CR 0xFFE38000
+
+/* bank 1 is main flash */
+/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB1AP 0x04850240
+/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
+#define CFG_EBC_PB1CR 0xF00FC000
+
+/* bank 2 is RTC/NVRAM */
+/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB2AP 0x03000440
+/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB2CR 0xFC018000
+
+/* bank 3 is FPGA 0 */
+/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
+#define CFG_EBC_PB3AP 0x02000400
+/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB3CR 0xFD01A000
+
+/* bank 4 is SAM 8 bit range */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CFG_EBC_PB4AP 0x02840380
+/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB4CR 0xFE878000
+
+/* bank 5 is SAM 16 bit range */
+/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
+#define CFG_EBC_PB5AP 0x05040d80
+/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB5CR 0xFD87A000
+
+/* bank 6 is unused */
+/* pb6ap = 0 */
+#define CFG_EBC_PB6AP 0x00000000
+/* pb6cr = 0 */
+#define CFG_EBC_PB6CR 0x00000000
+
+/* bank 7 is LED register */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB7AP 0x03050440
+/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
+#define CFG_W7O_EBC_PB7CR 0xFE01C000
+
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFFD0000
+#define CFG_FLASH_BASE 0xFFFC0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
-
/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in RAM)
*/
-#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
#define DTT_TEMP_HIGH 0xA1
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
-#en
+#endif
+
+#endif /* _DTT_H_ */
/* 8 64K x 8 uniform sectors */
#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
+#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B
* Bright Micro BM29F040
* Fujitsu MBM29F040A
+ * STM M29W040B
* SGS Thomson M29F040B
* 8 64K x 8 uniform sectors
*/
projects / users / rw / ppcboot.git / commitdiff