return 0;
 }
 
+#define KSZ8873MLL_GLOBAL_CONTROL_4    0x06
+#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX     (1 << 6)
+#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED      (1 << 4)
+int ksz8873mll_read_status(struct phy_device *phydev)
+{
+       int regval;
+
+       /* dummy read */
+       regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
+
+       regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
+
+       if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
+               phydev->duplex = DUPLEX_HALF;
+       else
+               phydev->duplex = DUPLEX_FULL;
+
+       if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
+               phydev->speed = SPEED_10;
+       else
+               phydev->speed = SPEED_100;
+
+       phydev->link = 1;
+       phydev->pause = phydev->asym_pause = 0;
+
+       return 0;
+}
+
+static int ksz8873mll_config_aneg(struct phy_device *phydev)
+{
+       return 0;
+}
+
 static struct phy_driver ksphy_driver[] = {
 {
        .phy_id         = PHY_ID_KS8737,
        .ack_interrupt  = kszphy_ack_interrupt,
        .config_intr    = ksz9021_config_intr,
        .driver         = { .owner = THIS_MODULE, },
+}, {
+       .phy_id         = PHY_ID_KSZ8873MLL,
+       .phy_id_mask    = 0x00fffff0,
+       .name           = "Micrel KSZ8873MLL Switch",
+       .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
+       .flags          = PHY_HAS_MAGICANEG,
+       .config_init    = kszphy_config_init,
+       .config_aneg    = ksz8873mll_config_aneg,
+       .read_status    = ksz8873mll_read_status,
+       .driver         = { .owner = THIS_MODULE, },
 } };
 
 static int __init ksphy_init(void)
        { PHY_ID_KSZ8021, 0x00ffffff },
        { PHY_ID_KSZ8041, 0x00fffff0 },
        { PHY_ID_KSZ8051, 0x00fffff0 },
+       { PHY_ID_KSZ8873MLL, 0x00fffff0 },
        { }
 };