#include "../thermal_core.h"
 #include "intel_hfi.h"
-
-#define THERM_STATUS_CLEAR_PKG_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | \
-                                    BIT(9) | BIT(11) | BIT(26))
+#include "thermal_interrupt.h"
 
 /* Hardware Feedback Interface MSR configuration bits */
 #define HW_FEEDBACK_PTR_VALID_BIT              BIT(0)
         * Let hardware know that we are done reading the HFI table and it is
         * free to update it again.
         */
-       pkg_therm_status_msr_val &= THERM_STATUS_CLEAR_PKG_MASK &
-                                   ~PACKAGE_THERM_STATUS_HFI_UPDATED;
-       wrmsrl(MSR_IA32_PACKAGE_THERM_STATUS, pkg_therm_status_msr_val);
+       thermal_clear_package_intr_status(PACKAGE_LEVEL, PACKAGE_THERM_STATUS_HFI_UPDATED);
 
        queue_delayed_work(hfi_updates_wq, &hfi_instance->update_work,
                           HFI_UPDATE_INTERVAL);
 
 };
 #endif /* CONFIG_SYSFS */
 
-#define CORE_LEVEL     0
-#define PACKAGE_LEVEL  1
-
 #define THERM_THROT_POLL_INTERVAL      HZ
 #define THERM_STATUS_PROCHOT_LOG       BIT(1)
 
 #define THERM_STATUS_CLEAR_CORE_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(13) | BIT(15))
 #define THERM_STATUS_CLEAR_PKG_MASK  (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(26))
 
-static void clear_therm_status_log(int level)
+/*
+ * Clear the bits in package thermal status register for bit = 1
+ * in bitmask
+ */
+void thermal_clear_package_intr_status(int level, u64 bit_mask)
 {
+       u64 msr_val;
        int msr;
-       u64 mask, msr_val;
 
        if (level == CORE_LEVEL) {
                msr  = MSR_IA32_THERM_STATUS;
-               mask = THERM_STATUS_CLEAR_CORE_MASK;
+               msr_val = THERM_STATUS_CLEAR_CORE_MASK;
        } else {
                msr  = MSR_IA32_PACKAGE_THERM_STATUS;
-               mask = THERM_STATUS_CLEAR_PKG_MASK;
+               msr_val = THERM_STATUS_CLEAR_PKG_MASK;
        }
 
-       rdmsrl(msr, msr_val);
-       msr_val &= mask;
-       wrmsrl(msr, msr_val & ~THERM_STATUS_PROCHOT_LOG);
+       msr_val &= ~bit_mask;
+       wrmsrl(msr, msr_val);
 }
+EXPORT_SYMBOL_GPL(thermal_clear_package_intr_status);
 
 static void get_therm_status(int level, bool *proc_hot, u8 *temp)
 {
        state->average = avg;
 
 re_arm:
-       clear_therm_status_log(state->level);
+       thermal_clear_package_intr_status(state->level, THERM_STATUS_PROCHOT_LOG);
        schedule_delayed_work_on(this_cpu, &state->therm_work, THERM_THROT_POLL_INTERVAL);
 }
 
 
 #ifndef _INTEL_THERMAL_INTERRUPT_H
 #define _INTEL_THERMAL_INTERRUPT_H
 
+#define CORE_LEVEL     0
+#define PACKAGE_LEVEL  1
+
 /* Interrupt Handler for package thermal thresholds */
 extern int (*platform_thermal_package_notify)(__u64 msr_val);
 
 /* Handle HWP interrupt */
 extern void notify_hwp_interrupt(void);
 
+/* Common function to clear Package thermal status register */
+extern void thermal_clear_package_intr_status(int level, u64 bit_mask);
+
 #endif /* _INTEL_THERMAL_INTERRUPT_H */
 
        struct thermal_zone_device *tzone = NULL;
        int cpu = smp_processor_id();
        struct zone_device *zonedev;
-       u64 msr_val, wr_val;
 
        mutex_lock(&thermal_zone_mutex);
        raw_spin_lock_irq(&pkg_temp_lock);
        }
        zonedev->work_scheduled = false;
 
-       rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
-       wr_val = msr_val & ~(THERM_LOG_THRESHOLD0 | THERM_LOG_THRESHOLD1);
-       if (wr_val != msr_val) {
-               wrmsrl(MSR_IA32_PACKAGE_THERM_STATUS, wr_val);
-               tzone = zonedev->tzone;
-       }
+       thermal_clear_package_intr_status(PACKAGE_LEVEL, THERM_LOG_THRESHOLD0 | THERM_LOG_THRESHOLD1);
+       tzone = zonedev->tzone;
 
        enable_pkg_thres_interrupt();
        raw_spin_unlock_irq(&pkg_temp_lock);