return 0;
 }
 
+void r100_set_common_regs(struct radeon_device *rdev)
+{
+       /* set these so they don't interfere with anything */
+       WREG32(RADEON_OV0_SCALE_CNTL, 0);
+       WREG32(RADEON_SUBPIC_CNTL, 0);
+       WREG32(RADEON_VIPH_CONTROL, 0);
+       WREG32(RADEON_I2C_CNTL_1, 0);
+       WREG32(RADEON_DVI_I2C_CNTL_1, 0);
+       WREG32(RADEON_CAP0_TRIG_CNTL, 0);
+       WREG32(RADEON_CAP1_TRIG_CNTL, 0);
+}
 
 /*
  * VRAM info
 {
        int r;
 
+       /* set common regs */
+       r100_set_common_regs(rdev);
+       /* program mc */
        r100_mc_program(rdev);
        /* Resume clock */
        r100_clock_startup(rdev);
 
                                struct radeon_cs_packet *pkt,
                                unsigned idx);
 extern void r100_enable_bm(struct radeon_device *rdev);
+extern void r100_set_common_regs(struct radeon_device *rdev);
 
 /* rv200,rv250,rv280 */
 extern void r200_set_safe_registers(struct radeon_device *rdev);