arm64: dts: renesas: r8a77961: Add CAN nodes

Add the device nodes for all CAN nodes on R-Car M3-W+.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Link: https://lore.kernel.org/r/20210312025420.529339-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index e8c31ebec09730c41591e09b09e39d9f028ea170..d44b7fef1e8ec58e46438220f5a23d63b7f1a68e 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -1155,13 +1155,35 @@
                };
 
                can0: can@e6c30000 {
+                       compatible = "renesas,can-r8a77961",
+                                    "renesas,rcar-gen3-can";
                        reg = <0 0xe6c30000 0 0x1000>;
-                       /* placeholder */
+                       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 916>,
+                              <&cpg CPG_CORE R8A77961_CLK_CANFD>,
+                              <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
+                       assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
+                       assigned-clock-rates = <40000000>;
+                       power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+                       resets = <&cpg 916>;
+                       status = "disabled";
                };
 
                can1: can@e6c38000 {
+                       compatible = "renesas,can-r8a77961",
+                                    "renesas,rcar-gen3-can";
                        reg = <0 0xe6c38000 0 0x1000>;
-                       /* placeholder */
+                       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 915>,
+                              <&cpg CPG_CORE R8A77961_CLK_CANFD>,
+                              <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
+                       assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
+                       assigned-clock-rates = <40000000>;
+                       power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+                       resets = <&cpg 915>;
+                       status = "disabled";
                };
 
                pwm0: pwm@e6e30000 {