drm/amdgpu/vcn:Update SPG mode VCN global tiling

Update Static Power Gate mode VCN global tiling

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 73301a9dc37da7171868ff7c215e780d016c4343..29f711b57506309917a8cfd0ed3b84348e2d99c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -325,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
                        adev->gfx.config.gb_addr_config);
        WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
                        adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
+                       adev->gfx.config.gb_addr_config);
 }
 
 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)