drm/amd/powerplay: enable clock gating for Fiji.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index c96b4580839f0dc9cb0d7b7d20e463029fa5966c..45997e609fd6cac37f782c3ec68cbd08f5e8276f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -917,7 +917,14 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
        }
 
        /* To initialize all clock gating before RLC loaded and running.*/
-       /*PECI_InitClockGating(peci);*/
+       cgs_set_clockgating_state(smumgr->device,
+                       AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
+       cgs_set_clockgating_state(smumgr->device,
+                       AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
+       cgs_set_clockgating_state(smumgr->device,
+                       AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
+       cgs_set_clockgating_state(smumgr->device,
+                       AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
 
        /* Setup SoftRegsStart here for register lookup in case
         * DummyBackEnd is used and ProcessFirmwareHeader is not executed