iommu: sun50i: clear bypass register

The Allwinner H6 IOMMU has a bypass register, which allows to circumvent
the page tables for each possible master. The reset value for this
register is 0, which disables the bypass.
The Allwinner H616 IOMMU resets this register to 0x7f, which activates
the bypass for all masters, which is not what we want.

Always clear this register to 0, to enforce the usage of page tables,
and make this driver compatible with the H616 in this respect.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20240616224056.29159-2-andre.przywara@arm.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index c519b991749d758b6d26cd2cb9effbeeb8fb6f73..dd3f07384624c51b1655b3377d8dfa5cd08906da 100644 (file)
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -452,6 +452,7 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
                    IOMMU_TLB_PREFETCH_MASTER_ENABLE(3) |
                    IOMMU_TLB_PREFETCH_MASTER_ENABLE(4) |
                    IOMMU_TLB_PREFETCH_MASTER_ENABLE(5));
+       iommu_write(iommu, IOMMU_BYPASS_REG, 0);
        iommu_write(iommu, IOMMU_INT_ENABLE_REG, IOMMU_INT_MASK);
        iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_NONE),
                    IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 0) |