reg |= XGBE_KR_TRAINING_ENABLE;
        reg |= XGBE_KR_TRAINING_START;
        XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+       pdata->kr_start_time = jiffies;
 
        netif_dbg(pdata, link, pdata->netdev,
                  "KR training initiated\n");
 
        xgbe_switch_mode(pdata);
 
+       pdata->an_result = XGBE_AN_READY;
+
        xgbe_an_restart(pdata);
 
        return XGBE_AN_INCOMPAT_LINK;
 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
 {
        unsigned long link_timeout;
+       unsigned long kr_time;
+       int wait;
 
        link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
        if (time_after(jiffies, link_timeout)) {
+               if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
+                   pdata->phy.autoneg == AUTONEG_ENABLE) {
+                       /* AN restart should not happen while KR training is in progress.
+                        * The while loop ensures no AN restart during KR training,
+                        * waits up to 500ms and AN restart is triggered only if KR
+                        * training is failed.
+                        */
+                       wait = XGBE_KR_TRAINING_WAIT_ITER;
+                       while (wait--) {
+                               kr_time = pdata->kr_start_time +
+                                         msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
+                               if (time_after(jiffies, kr_time))
+                                       break;
+                               /* AN restart is not required, if AN result is COMPLETE */
+                               if (pdata->an_result == XGBE_AN_COMPLETE)
+                                       return;
+                               usleep_range(10000, 11000);
+                       }
+               }
                netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
                xgbe_phy_config_aneg(pdata);
        }
 
 /* Auto-negotiation */
 #define XGBE_AN_MS_TIMEOUT             500
 #define XGBE_LINK_TIMEOUT              5
+#define XGBE_KR_TRAINING_WAIT_ITER     50
 
 #define XGBE_SGMII_AN_LINK_STATUS      BIT(1)
 #define XGBE_SGMII_AN_LINK_SPEED       (BIT(2) | BIT(3))
        unsigned int parallel_detect;
        unsigned int fec_ability;
        unsigned long an_start;
+       unsigned long kr_start_time;
        enum xgbe_an_mode an_mode;
 
        /* I2C support */