drm/amd/pp: Implement force_dpm_level on Rv

user can change dpm level on Rv through sysfs

v3: add smu version check
v2: fix no return statement

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index ae11a85bf220ca7202050f8c5e0c204e933deb0e..569073e3a5a1372485caf56976d83479e4330fa4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -484,6 +484,129 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
                                enum amd_dpm_forced_level level)
 {
+       if (hwmgr->smu_version < 0x1E3700) {
+               pr_info("smu firmware version too old, can not set dpm level\n");
+               return 0;
+       }
+
+       switch (level) {
+       case AMD_DPM_FORCED_LEVEL_HIGH:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinGfxClk,
+                                               RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinFclkByFreq,
+                                               RAVEN_UMD_PSTATE_PEAK_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinSocclkByFreq,
+                                               RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinVcn,
+                                               RAVEN_UMD_PSTATE_VCE);
+
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxGfxClk,
+                                               RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxFclkByFreq,
+                                               RAVEN_UMD_PSTATE_PEAK_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxSocclkByFreq,
+                                               RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxVcn,
+                                               RAVEN_UMD_PSTATE_VCE);
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinGfxClk,
+                                               RAVEN_UMD_PSTATE_MIN_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxGfxClk,
+                                               RAVEN_UMD_PSTATE_MIN_GFXCLK);
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinFclkByFreq,
+                                               RAVEN_UMD_PSTATE_MIN_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxFclkByFreq,
+                                               RAVEN_UMD_PSTATE_MIN_FCLK);
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinGfxClk,
+                                               RAVEN_UMD_PSTATE_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinFclkByFreq,
+                                               RAVEN_UMD_PSTATE_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinSocclkByFreq,
+                                               RAVEN_UMD_PSTATE_SOCCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinVcn,
+                                               RAVEN_UMD_PSTATE_VCE);
+
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxGfxClk,
+                                               RAVEN_UMD_PSTATE_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxFclkByFreq,
+                                               RAVEN_UMD_PSTATE_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxSocclkByFreq,
+                                               RAVEN_UMD_PSTATE_SOCCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxVcn,
+                                               RAVEN_UMD_PSTATE_VCE);
+               break;
+       case AMD_DPM_FORCED_LEVEL_AUTO:
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinGfxClk,
+                                               RAVEN_UMD_PSTATE_MIN_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinFclkByFreq,
+                                               RAVEN_UMD_PSTATE_MIN_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinSocclkByFreq,
+                                               RAVEN_UMD_PSTATE_MIN_SOCCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinVcn,
+                                               RAVEN_UMD_PSTATE_MIN_VCE);
+
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxGfxClk,
+                                               RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxFclkByFreq,
+                                               RAVEN_UMD_PSTATE_PEAK_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxSocclkByFreq,
+                                               RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxVcn,
+                                               RAVEN_UMD_PSTATE_VCE);
+               break;
+       case AMD_DPM_FORCED_LEVEL_LOW:
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinGfxClk,
+                                               RAVEN_UMD_PSTATE_MIN_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxGfxClk,
+                                               RAVEN_UMD_PSTATE_MIN_GFXCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetHardMinFclkByFreq,
+                                               RAVEN_UMD_PSTATE_MIN_FCLK);
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetSoftMaxFclkByFreq,
+                                               RAVEN_UMD_PSTATE_MIN_FCLK);
+               break;
+       case AMD_DPM_FORCED_LEVEL_MANUAL:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+       default:
+               break;
+       }
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 9dc50305539468929663f5887d000ba9ae5521ef..c3bc311dc59ff3e3894f5ca221faecfcc0768c9f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -304,4 +304,19 @@ struct pp_hwmgr;
 
 int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
 
+/* UMD PState Raven Msg Parameters in MHz */
+#define RAVEN_UMD_PSTATE_GFXCLK                 700
+#define RAVEN_UMD_PSTATE_SOCCLK                 626
+#define RAVEN_UMD_PSTATE_FCLK                   933
+#define RAVEN_UMD_PSTATE_VCE                    0x03C00320
+
+#define RAVEN_UMD_PSTATE_PEAK_GFXCLK            1100
+#define RAVEN_UMD_PSTATE_PEAK_SOCCLK            757
+#define RAVEN_UMD_PSTATE_PEAK_FCLK              1200
+
+#define RAVEN_UMD_PSTATE_MIN_GFXCLK             200
+#define RAVEN_UMD_PSTATE_MIN_FCLK               400
+#define RAVEN_UMD_PSTATE_MIN_SOCCLK             200
+#define RAVEN_UMD_PSTATE_MIN_VCE                0x0190012C
+
 #endif