This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).
Imported from
https://github.com/riscv-collab/riscv-openocd/pull/752
Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8911
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Bernhard Rosenkränzer <bero@baylibre.com>
{ .name = "halted", .value = TARGET_HALTED },
{ .name = "reset", .value = TARGET_RESET },
{ .name = "debug-running", .value = TARGET_DEBUG_RUNNING },
+ { .name = "unavailable", .value = TARGET_UNAVAILABLE },
{ .name = NULL, .value = -1 },
};
* not sure how this is used with all the recent changes)
* TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
* behalf of the debugger (e.g. algorithm for flashing)
+ * TARGET_UNAVAILABLE = 5: The target is unavailable for some reason. It might
+ * be powered down, for instance.
*
* also see: target_state_name();
*/
TARGET_HALTED = 2,
TARGET_RESET = 3,
TARGET_DEBUG_RUNNING = 4,
+ TARGET_UNAVAILABLE = 5
};
enum target_reset_mode {