ARM: dts: imx6qdl: add phy-3p0-supply to usb phys

The integrated usb phys are supplied by the 3p0 regulator, which has a
voltage range of 2.625V to 3.4V. Thus the min and max values are
corrected and the regulator added as a proper supply for the usb phys.

This fixes the following warnings during the probe of the mxs_phy
driver:

mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator
mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator

The 3p0 regulator handling was introduced by commit 966d73152078 ("usb:
phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`.

Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index d2200c9db25aec90dbd348dedee4bfef47eb3ee7..45bcfd7faf9db628479359b5c0a26e1011a7c2d3 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -711,8 +711,8 @@
                                reg_vdd3p0: regulator-3p0 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
-                                       regulator-min-microvolt = <2800000>;
-                                       regulator-max-microvolt = <3150000>;
+                                       regulator-min-microvolt = <2625000>;
+                                       regulator-max-microvolt = <3400000>;
                                        regulator-always-on;
                                        anatop-reg-offset = <0x120>;
                                        anatop-vol-bit-shift = <8>;
@@ -806,6 +806,7 @@
                                reg = <0x020c9000 0x1000>;
                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+                               phy-3p0-supply = <&reg_vdd3p0>;
                                fsl,anatop = <&anatop>;
                        };
 
@@ -814,6 +815,7 @@
                                reg = <0x020ca000 0x1000>;
                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+                               phy-3p0-supply = <&reg_vdd3p0>;
                                fsl,anatop = <&anatop>;
                        };