ring = &adev->vcn.ring_dec;
                                WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
-                                                  RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));
+                                                  RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
                                SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
                                                   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
                                                   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
 
                                ring = &adev->vcn.ring_dec;
                                WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
-                                                  RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2));
+                                                  RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
                                SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
                                                   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
                                                   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);