]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4
authorAapo Vienamo <avienamo@nvidia.com>
Fri, 10 Aug 2018 18:08:42 +0000 (21:08 +0300)
committerThierry Reding <treding@nvidia.com>
Mon, 27 Aug 2018 10:27:31 +0000 (12:27 +0200)
Use assigned-clock properties to configure pllc4 as the parent clock
for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than
the default pllp and is required by HS200 and HS400 modes.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra210.dtsi

index 0951acc69cc8b3b0d7fe31dfe64b8ace431befc3..14da98ac65e88fd0a164de3a97c2bc3efc1a50a2 100644 (file)
                nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
                nvidia,default-tap = <0x2>;
                nvidia,default-trim = <0x4>;
+               assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+                                 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
+                                 <&tegra_car TEGRA210_CLK_PLL_C4>;
+               assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+               assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
                status = "disabled";
        };
 
                nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
                nvidia,default-tap = <0x8>;
                nvidia,default-trim = <0x0>;
+               assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+                                 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+               assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
                status = "disabled";
        };