x86/cpu/AMD: Make the LFENCE instruction serialized

In order to reduce the impact of using MFENCE, make the execution of the
LFENCE instruction serialized.  This is done by setting bit 1 of MSR
0xc0011029 (DE_CFG).

Some families that support LFENCE do not have this MSR.  For these
families, the LFENCE instruction is already serialized.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Orabug: 27340445
CVE: CVE-2017-5753

Signed-off-by: Chuck Anderson <chuck.anderson@oracle.com>
Conflicts:
	patch refers to arch/x86/include/asm/msr-index.h
	code base has arch/x86/include/uapi/asm/msr-index.h

Reviewed-by: John Haxby <john.haxby@oracle.com>
Signed-off-by: Kirtikar Kashyap <kirtikar.kashyap@oracle.com>

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 50df8b9920158979f68db5ee763c1bae85a36e7f..a4d88b896b55e8da6c432d724e481fc37abb4370 100644 (file)
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -326,6 +326,8 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
+#define MSR_F10H_DECFG                 0xc0011029
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e4cf63301ff439ed390e50a81a72fef9ea50e23a..5d9632f267a7369f6fccaf9163204a37522a3521 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -700,8 +700,17 @@ static void init_amd(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_K8);
 
        if (cpu_has_xmm2) {
-               /* MFENCE stops RDTSC speculation */
-               set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
+               /*
+                * Use LFENCE for execution serialization. On some families
+                * LFENCE is already serialized and the MSR is not available,
+                * but msr_set_bit() uses rdmsrl_safe() and wrmsrl_safe().
+                */
+               if (c->x86 > 0xf)
+                       msr_set_bit(MSR_F10H_DECFG,
+                                   MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+
+               /* LFENCE with MSR_F10H_DECFG[1]=1 stops RDTSC speculation */
+               set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
        }
 
        /*