ARM: dts: r7s9210: Add RSPI

Add RSPI support for RZ/A2 SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 22baa96f597454cb5182b9e3b0256498faf970df..8423004bb4b7fe3aa46976edb0f0ba0cec3322e4 100644 (file)
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -146,6 +146,51 @@
                        status = "disabled";
                };
 
+               spi0: spi@e800c800 {
+                       compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+                       reg = <0xe800c800 0x24>;
+                       interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error", "rx", "tx";
+                       clocks = <&cpg CPG_MOD 97>;
+                       power-domains = <&cpg>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi1: spi@e800d000 {
+                       compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+                       reg = <0xe800d000 0x24>;
+                       interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error", "rx", "tx";
+                       clocks = <&cpg CPG_MOD 96>;
+                       power-domains = <&cpg>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi2: spi@e800d800 {
+                       compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+                       reg = <0xe800d800 0x24>;
+                       interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "error", "rx", "tx";
+                       clocks = <&cpg CPG_MOD 95>;
+                       power-domains = <&cpg>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                ostm0: timer@e803b000 {
                        compatible = "renesas,r7s9210-ostm", "renesas,ostm";
                        reg = <0xe803b000 0x30>;