]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/i915: pass dev_priv explicitly to PRIMPOS
authorJani Nikula <jani.nikula@intel.com>
Thu, 23 May 2024 12:59:41 +0000 (15:59 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 24 May 2024 07:41:12 +0000 (10:41 +0300)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PRIMPOS register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4bbb3218ac25b292bea46dcba3df8ec474d578e2.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/i9xx_plane.c
drivers/gpu/drm/i915/display/i9xx_plane_regs.h

index 2026323d88ac2c4d74251cb0b0f4058325ebeb3d..1cefcdd4f26af597ef695acd55da2db834749d0a 100644 (file)
@@ -474,7 +474,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
                int crtc_w = drm_rect_width(&plane_state->uapi.dst);
                int crtc_h = drm_rect_height(&plane_state->uapi.dst);
 
-               intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
+               intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane),
                                  PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
                intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
                                  PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
index f67c5a2bb6b929cdd6d3fb665f24d075ed2a112a..7f291b34f10a1264fbec943fabad8ac29a1e9c78 100644 (file)
@@ -87,8 +87,8 @@
 #define DSPGAMC(dev_priv, plane, i)            _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
 
 /* CHV pipe B primary plane */
-#define _PRIMPOS_A             0x60a08
-#define PRIMPOS(plane)         _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
+#define _PRIMPOS_A                     0x60a08
+#define PRIMPOS(dev_priv, plane)       _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
 #define   PRIM_POS_Y_MASK      REG_GENMASK(31, 16)
 #define   PRIM_POS_Y(y)                REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
 #define   PRIM_POS_X_MASK      REG_GENMASK(15, 0)