plat->bus_id = 1;
        plat->phy_addr = 0;
-       plat->interface = PHY_INTERFACE_MODE_GMII;
+       plat->phy_interface = PHY_INTERFACE_MODE_GMII;
 
        plat->dma_cfg->pbl = 32;
        plat->dma_cfg->pblx8 = true;
 {
        plat->bus_id = 1;
        plat->phy_addr = 0;
-       plat->interface = PHY_INTERFACE_MODE_SGMII;
+       plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+
        return ehl_common_data(pdev, plat);
 }
 
 {
        plat->bus_id = 1;
        plat->phy_addr = 0;
-       plat->interface = PHY_INTERFACE_MODE_RGMII;
+       plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
+
        return ehl_common_data(pdev, plat);
 }
 
 {
        plat->bus_id = 1;
        plat->phy_addr = 0;
-       plat->interface = PHY_INTERFACE_MODE_SGMII;
+       plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
        return tgl_common_data(pdev, plat);
 }
 
 
        plat->bus_id = pci_dev_id(pdev);
        plat->phy_addr = ret;
-       plat->interface = PHY_INTERFACE_MODE_RMII;
+       plat->phy_interface = PHY_INTERFACE_MODE_RMII;
 
        plat->dma_cfg->pbl = 16;
        plat->dma_cfg->pblx8 = true;
 
        plat->bus_id = 1;
        plat->phy_addr = -1;
-       plat->interface = PHY_INTERFACE_MODE_GMII;
+       plat->phy_interface = PHY_INTERFACE_MODE_GMII;
 
        plat->dma_cfg->pbl = 32;
        plat->dma_cfg->pblx8 = true;