*/
 static void goya_disable_external_queues(struct hl_device *hdev)
 {
+       struct goya_device *goya = hdev->asic_specific;
+
+       if (!(goya->hw_cap_initialized & HW_CAP_DMA))
+               return;
+
        WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
        WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
        WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
 {
        int rc, retval = 0;
 
+       struct goya_device *goya = hdev->asic_specific;
+
+       if (!(goya->hw_cap_initialized & HW_CAP_DMA))
+               return retval;
+
        rc = goya_stop_queue(hdev,
                        mmDMA_QM_0_GLBL_CFG1,
                        mmDMA_QM_0_CP_STS,
  */
 static void goya_disable_internal_queues(struct hl_device *hdev)
 {
+       struct goya_device *goya = hdev->asic_specific;
+
+       if (!(goya->hw_cap_initialized & HW_CAP_MME))
+               goto disable_tpc;
+
        WREG32(mmMME_QM_GLBL_CFG0, 0);
        WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
 
+disable_tpc:
+       if (!(goya->hw_cap_initialized & HW_CAP_TPC))
+               return;
+
        WREG32(mmTPC0_QM_GLBL_CFG0, 0);
        WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
 
  */
 static int goya_stop_internal_queues(struct hl_device *hdev)
 {
+       struct goya_device *goya = hdev->asic_specific;
        int rc, retval = 0;
 
+       if (!(goya->hw_cap_initialized & HW_CAP_MME))
+               goto stop_tpc;
+
        /*
         * Each queue (QMAN) is a separate H/W logic. That means that each
         * QMAN can be stopped independently and failure to stop one does NOT
                retval = -EIO;
        }
 
+stop_tpc:
+       if (!(goya->hw_cap_initialized & HW_CAP_TPC))
+               return retval;
+
        rc = goya_stop_queue(hdev,
                        mmTPC0_QM_GLBL_CFG1,
                        mmTPC0_QM_CP_STS,
 
 static void goya_dma_stall(struct hl_device *hdev)
 {
+       struct goya_device *goya = hdev->asic_specific;
+
+       if (!(goya->hw_cap_initialized & HW_CAP_DMA))
+               return;
+
        WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
        WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
        WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
 
 static void goya_tpc_stall(struct hl_device *hdev)
 {
+       struct goya_device *goya = hdev->asic_specific;
+
+       if (!(goya->hw_cap_initialized & HW_CAP_TPC))
+               return;
+
        WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
        WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
        WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
 
 static void goya_mme_stall(struct hl_device *hdev)
 {
+       struct goya_device *goya = hdev->asic_specific;
+
+       if (!(goya->hw_cap_initialized & HW_CAP_MME))
+               return;
+
        WREG32(mmMME_STALL, 0xFFFFFFFF);
 }