drm:amdgpu: enable IH ring1 for IH v7.0

We need IH ring1 for handling the pagefault
interrupts which over flow in default
ring for specific usecases.

Enable ring1 allows software to redirect
high interrupts to ring1 from default IH
ring.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index aa6235dd4f2b0b10a76f26778140ef62bcea2f73..548b3c63a76592e229ff2181a5ea479ee0ae4f75 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -546,8 +546,15 @@ static int ih_v7_0_sw_init(void *handle)
        adev->irq.ih.use_doorbell = true;
        adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-       adev->irq.ih1.ring_size = 0;
-       adev->irq.ih2.ring_size = 0;
+       if (!(adev->flags & AMD_IS_APU)) {
+               r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
+                                       use_bus_addr);
+               if (r)
+                       return r;
+
+               adev->irq.ih1.use_doorbell = true;
+               adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
+       }
 
        /* initialize ih control register offset */
        ih_v7_0_init_register_offset(adev);