&hw_ci, sizeof(hw_ci), NULL,
                                 NULL, HINIC_MGMT_MSG_SYNC);
 }
+
+/**
+ * hinic_hwdev_set_msix_state- set msix state
+ * @hwdev: the NIC HW device
+ * @msix_index: IRQ corresponding index number
+ * @flag: msix state
+ *
+ **/
+void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
+                               enum hinic_msix_state flag)
+{
+       hinic_set_msix_state(hwdev->hwif, msix_index, flag);
+}
 
 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
                               u8 pending_limit, u8 coalesc_timer);
 
+void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
+                               enum hinic_msix_state flag);
+
 #endif
 
        hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4);
 }
 
+void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
+                         enum hinic_msix_state flag)
+{
+       u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE +
+                       HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL;
+       u32 mask_bits;
+
+       mask_bits = readl(hwif->intr_regs_base + offset);
+       mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;
+
+       if (flag)
+               mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;
+
+       writel(mask_bits, hwif->intr_regs_base + offset);
+}
+
 /**
  * hwif_ready - test if the HW is ready for use
  * @hwif: the HW interface of a pci function device
                return -ENOMEM;
        }
 
+       hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR);
+       if (!hwif->intr_regs_base) {
+               dev_err(&pdev->dev, "Failed to map configuration regs\n");
+               err = -ENOMEM;
+               goto err_map_intr_bar;
+       }
+
        err = hwif_ready(hwif);
        if (err) {
                dev_err(&pdev->dev, "HW interface is not ready\n");
        return 0;
 
 err_hwif_ready:
+       iounmap(hwif->intr_regs_base);
+
+err_map_intr_bar:
        iounmap(hwif->cfg_regs_bar);
+
        return err;
 }
 
  **/
 void hinic_free_hwif(struct hinic_hwif *hwif)
 {
+       iounmap(hwif->intr_regs_base);
        iounmap(hwif->cfg_regs_bar);
 }
 
 #define HINIC_IS_PPF(hwif)              (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
 
 #define HINIC_PCI_CFG_REGS_BAR          0
+#define HINIC_PCI_INTR_REGS_BAR         2
 #define HINIC_PCI_DB_BAR                4
 
 #define HINIC_PCIE_ST_DISABLE           0
 #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT  0       /* Disabled */
 #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT      7       /* max */
 
+#define HINIC_PCI_MSIX_ENTRY_SIZE               16
+#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL        12
+#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT       1
+
 enum hinic_pcie_nosnoop {
        HINIC_PCIE_SNOOP        = 0,
        HINIC_PCIE_NO_SNOOP     = 1,
        HINIC_DB_DISABLE = 1,
 };
 
+enum hinic_msix_state {
+       HINIC_MSIX_ENABLE,
+       HINIC_MSIX_DISABLE,
+};
+
 struct hinic_func_attr {
        u16                     func_idx;
        u8                      pf_idx;
 struct hinic_hwif {
        struct pci_dev          *pdev;
        void __iomem            *cfg_regs_bar;
+       void __iomem            *intr_regs_base;
 
        struct hinic_func_attr  attr;
 };
                        u8 *lli_timer, u8 *lli_credit_limit,
                        u8 *resend_timer);
 
+void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
+                         enum hinic_msix_state flag);
+
 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
 
 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);
 
 static int rx_poll(struct napi_struct *napi, int budget)
 {
        struct hinic_rxq *rxq = container_of(napi, struct hinic_rxq, napi);
+       struct hinic_dev *nic_dev = netdev_priv(rxq->netdev);
        struct hinic_rq *rq = rxq->rq;
        int pkts;
 
                return budget;
 
        napi_complete(napi);
-       enable_irq(rq->irq);
+       hinic_hwdev_set_msix_state(nic_dev->hwdev,
+                                  rq->msix_entry,
+                                  HINIC_MSIX_ENABLE);
+
        return pkts;
 }
 
        struct hinic_dev *nic_dev;
 
        /* Disable the interrupt until napi will be completed */
-       disable_irq_nosync(rq->irq);
+       nic_dev = netdev_priv(rxq->netdev);
+       hinic_hwdev_set_msix_state(nic_dev->hwdev,
+                                  rq->msix_entry,
+                                  HINIC_MSIX_DISABLE);
 
        nic_dev = netdev_priv(rxq->netdev);
        hinic_hwdev_msix_cnt_set(nic_dev->hwdev, rq->msix_entry);
 
 
        if (pkts < budget) {
                napi_complete(napi);
-               enable_irq(sq->irq);
+               hinic_hwdev_set_msix_state(nic_dev->hwdev,
+                                          sq->msix_entry,
+                                          HINIC_MSIX_ENABLE);
                return pkts;
        }
 
        nic_dev = netdev_priv(txq->netdev);
 
        /* Disable the interrupt until napi will be completed */
-       disable_irq_nosync(txq->sq->irq);
+       hinic_hwdev_set_msix_state(nic_dev->hwdev,
+                                  txq->sq->msix_entry,
+                                  HINIC_MSIX_DISABLE);
 
        hinic_hwdev_msix_cnt_set(nic_dev->hwdev, txq->sq->msix_entry);