{
        __reset_rsvds_bits_mask(&context->guest_rsvd_check,
                                vcpu->arch.reserved_gpa_bits,
-                               context->root_level, context->nx,
+                               context->root_level, is_efer_nx(context),
                                guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
                                is_cr4_pse(context),
                                guest_cpuid_is_amd_or_hygon(vcpu));
         * NX can be used by any non-nested shadow MMU to avoid having to reset
         * MMU contexts.  Note, KVM forces EFER.NX=1 when TDP is disabled.
         */
-       bool uses_nx = context->nx || !tdp_enabled;
+       bool uses_nx = is_efer_nx(context) || !tdp_enabled;
 
        /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
        bool is_amd = true;
        bool cr4_smep = is_cr4_smep(mmu);
        bool cr4_smap = is_cr4_smap(mmu);
        bool cr0_wp = is_cr0_wp(mmu);
+       bool efer_nx = is_efer_nx(mmu);
 
        for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
                unsigned pfec = byte << 1;
                        u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
 
                        /* Not really needed: !nx will cause pte.nx to fault */
-                       if (!mmu->nx)
+                       if (!efer_nx)
                                ff = 0;
 
                        /* Allow supervisor writes if !cr0.wp */