};
 
 #define NUM_PFI_CHANNELS 40
-/* really there are only up to 3 dma channels, but the register layout allows for 4 */
+/* really there are only up to 3 dma channels, but the register layout allows
+for 4 */
+
 #define MAX_DMA_CHANNEL 4
 
 /* See Register-Level Programmer Manual page 3.1 */
        const char *name;       /*  Register Name */
        int offset;             /*  Offset from base address from GPCT chip */
        enum ni_660x_register_direction direction;
-       enum ni_660x_register_width size;       /*  1 byte, 2 bytes, or 4 bytes */
+       enum ni_660x_register_width size; /*  1 byte, 2 bytes, or 4 bytes */
 };
 
 static const struct NI_660xRegisterData registerData[NumRegisters] = {
 };
 
 /* Offset of the GPCT chips from the base-adress of the card */
-static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* First chip is at base-address +
-                                                          0x00, etc. */
+/* First chip is at base-address + 0x00, etc. */
+static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
 
 /* Board description*/
 struct ni_660x_board {
                ni_660x_register = G3InterruptEnable;
                break;
        default:
-               printk("%s: unhandled register 0x%x in switch.\n",
+               printk(KERN_WARNING "%s: unhandled register 0x%x in switch.\n",
                       __func__, reg);
                BUG();
                return 0;
                writel(bits, write_address);
                break;
        default:
-               printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
+               printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
                       __FILE__, __func__, reg);
                BUG();
                break;
                return readl(read_address);
                break;
        default:
-               printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
+               printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
                       __FILE__, __func__, reg);
                BUG();
                break;
        spin_lock_init(&private(dev)->mite_channel_lock);
        spin_lock_init(&private(dev)->interrupt_lock);
        spin_lock_init(&private(dev)->soft_reg_copy_lock);
-       for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
+       for (i = 0; i < NUM_PFI_CHANNELS; ++i)
                private(dev)->pfi_output_selects[i] = pfi_output_select_counter;
-       }
+
        return 0;
 }
 
                for (j = 0; j < counters_per_chip; ++j) {
                        private(dev)->mite_rings[i][j] =
                            mite_alloc_ring(private(dev)->mite);
-                       if (private(dev)->mite_rings[i][j] == NULL) {
+                       if (private(dev)->mite_rings[i][j] == NULL)
                                return -ENOMEM;
-                       }
                }
        }
        return 0;
        unsigned j;
 
        for (i = 0; i < board(dev)->n_chips; ++i) {
-               for (j = 0; j < counters_per_chip; ++j) {
+               for (j = 0; j < counters_per_chip; ++j)
                        mite_free_ring(private(dev)->mite_rings[i][j]);
-               }
        }
 }
 
        unsigned i;
        unsigned global_interrupt_config_bits;
 
-       printk("comedi%d: ni_660x: ", dev->minor);
+       printk(KERN_INFO "comedi%d: ni_660x: ", dev->minor);
 
        ret = ni_660x_allocate_private(dev);
        if (ret < 0)
 
        ret = mite_setup2(private(dev)->mite, 1);
        if (ret < 0) {
-               printk("error setting up mite\n");
+               printk(KERN_WARNING "error setting up mite\n");
                return ret;
        }
        comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev);
        if (ret < 0)
                return ret;
 
-       printk(" %s ", dev->board_name);
+       printk(KERN_INFO " %s ", dev->board_name);
 
        dev->n_subdevices = 2 + NI_660X_MAX_NUM_COUNTERS;
 
        s->insn_bits = ni_660x_dio_insn_bits;
        s->insn_config = ni_660x_dio_insn_config;
        s->io_bits = 0;         /* all bits default to input */
-       /*  we use the ioconfig registers to control dio direction, so zero output enables in stc dio control reg */
+       /*  we use the ioconfig registers to control dio direction, so zero
+       output enables in stc dio control reg */
        ni_660x_write_register(dev, 0, 0, STCDIOControl);
 
-       private(dev)->counter_dev = ni_gpct_device_construct(dev,
-                                                            &ni_gpct_write_register,
-                                                            &ni_gpct_read_register,
-                                                            ni_gpct_variant_660x,
-                                                            ni_660x_num_counters
-                                                            (dev));
+       private(dev)->counter_dev
+               = ni_gpct_device_construct(dev,
+                                          &ni_gpct_write_register,
+                                          &ni_gpct_read_register,
+                                          ni_gpct_variant_660x,
+                                          ni_660x_num_counters
+                                          (dev));
        if (private(dev)->counter_dev == NULL)
                return -ENOMEM;
        for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
                        s->type = COMEDI_SUBD_UNUSED;
                }
        }
-       for (i = 0; i < board(dev)->n_chips; ++i) {
+       for (i = 0; i < board(dev)->n_chips; ++i)
                init_tio_chip(dev, i);
-       }
-       for (i = 0; i < ni_660x_num_counters(dev); ++i) {
+
+       for (i = 0; i < ni_660x_num_counters(dev); ++i)
                ni_tio_init_counter(&private(dev)->counter_dev->counters[i]);
-       }
+
        for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
                if (i < min_counter_pfi_chan)
                        ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
        }
        /* to be safe, set counterswap bits on tio chips after all the counter
           outputs have been set to high impedance mode */
-       for (i = 0; i < board(dev)->n_chips; ++i) {
+       for (i = 0; i < board(dev)->n_chips; ++i)
                set_tio_counterswap(dev, i);
-       }
+
        ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt,
                          IRQF_SHARED, "ni_660x", dev);
        if (ret < 0) {
-               printk(" irq not available\n");
+               printk(KERN_WARNING " irq not available\n");
                return ret;
        }
        dev->irq = mite_irq(private(dev)->mite);
                global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
        ni_660x_write_register(dev, 0, global_interrupt_config_bits,
                               GlobalInterruptConfigRegister);
-       printk("attached\n");
+       printk(KERN_INFO "attached\n");
        return 0;
 }
 
 static int ni_660x_detach(struct comedi_device *dev)
 {
-       printk("comedi%d: ni_660x: remove\n", dev->minor);
+       printk(KERN_INFO "comedi%d: ni_660x: remove\n", dev->minor);
 
        /* Free irq */
        if (dev->irq)
                               private(dev)->
                               dma_configuration_soft_copies[chipset],
                               DMAConfigRegister);
-       for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
+       for (i = 0; i < NUM_PFI_CHANNELS; ++i)
                ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
-       }
 }
 
 static int
                        }
                }
        }
-       printk("no device found\n");
+       printk(KERN_WARNING "no device found\n");
        mite_list_devices();
        return -EIO;
 }