ARM: dts: r8a7791: Add L2 cache-controller node

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index f1732dde114b96422775f2a0e1e422b0b865e34b..6439f0569fe2c578bc26e66b97947fb7cf220dd9 100644 (file)
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
                        voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg_clocks R8A7791_CLK_Z>;
                        clock-latency = <300000>; /* 300 us */
+                       next-level-cache = <&L2_CA15>;
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1500000 1000000>,
@@ -66,6 +67,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <1>;
                        clock-frequency = <1500000000>;
+                       next-level-cache = <&L2_CA15>;
                };
        };
 
@@ -88,6 +90,12 @@
                };
        };
 
+       L2_CA15: cache-controller@0 {
+               compatible = "cache";
+               cache-unified;
+               cache-level = <2>;
+       };
+
        gic: interrupt-controller@f1001000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;