.verify = NULL,
                .wrapper = NULL
        },
+       /* flow steering commands */
+       {
+               .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
+               .has_inbox = true,
+               .has_outbox = false,
+               .out_is_imm = true,
+               .encode_slave_id = false,
+               .verify = NULL,
+               .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
+       },
+       {
+               .opcode = MLX4_QP_FLOW_STEERING_DETACH,
+               .has_inbox = false,
+               .has_outbox = false,
+               .out_is_imm = false,
+               .encode_slave_id = false,
+               .verify = NULL,
+               .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
+       },
 };
 
 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 
        return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
 }
 
+static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
+                                       struct mlx4_cmd_mailbox *mailbox,
+                                       u32 size,
+                                       u64 *reg_id)
+{
+       u64 imm;
+       int err = 0;
+
+       err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
+                          MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
+                          MLX4_CMD_NATIVE);
+       if (err)
+               return err;
+       *reg_id = imm;
+
+       return err;
+}
+
+static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
+{
+       int err = 0;
+
+       err = mlx4_cmd(dev, regid, 0, 0,
+                      MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
+                      MLX4_CMD_NATIVE);
+
+       return err;
+}
+
 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
                           struct mlx4_cmd_mailbox *mailbox)
 {
 
                               struct mlx4_cmd_mailbox *inbox,
                               struct mlx4_cmd_mailbox *outbox,
                               struct mlx4_cmd_info *cmd);
+int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
+                                        struct mlx4_vhcr *vhcr,
+                                        struct mlx4_cmd_mailbox *inbox,
+                                        struct mlx4_cmd_mailbox *outbox,
+                                        struct mlx4_cmd_info *cmd);
+int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
+                                        struct mlx4_vhcr *vhcr,
+                                        struct mlx4_cmd_mailbox *inbox,
+                                        struct mlx4_cmd_mailbox *outbox,
+                                        struct mlx4_cmd_info *cmd);
 
 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
 
        return err;
 }
 
+int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
+                                        struct mlx4_vhcr *vhcr,
+                                        struct mlx4_cmd_mailbox *inbox,
+                                        struct mlx4_cmd_mailbox *outbox,
+                                        struct mlx4_cmd_info *cmd)
+{
+       return mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
+                           vhcr->in_modifier, 0,
+                           MLX4_QP_FLOW_STEERING_ATTACH,
+                           MLX4_CMD_TIME_CLASS_A,
+                           MLX4_CMD_NATIVE);
+}
+
+int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
+                                        struct mlx4_vhcr *vhcr,
+                                        struct mlx4_cmd_mailbox *inbox,
+                                        struct mlx4_cmd_mailbox *outbox,
+                                        struct mlx4_cmd_info *cmd)
+{
+       return mlx4_cmd(dev, vhcr->in_param, 0, 0,
+                       MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
+                       MLX4_CMD_NATIVE);
+}
+
 enum {
        BUSY_MAX_RETRIES = 10
 };
 
        /* set port opcode modifiers */
        MLX4_SET_PORT_PRIO2TC = 0x8,
        MLX4_SET_PORT_SCHEDULER  = 0x9,
+
+       /* register/delete flow steering network rules */
+       MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
+       MLX4_QP_FLOW_STEERING_DETACH = 0x66,
 };
 
 enum {