"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS
Signed-off-by: Jihed Chaibi <jihed.chaibi.dev@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS                               0x10
 
 /**********************************************************************************************************************
   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
 
                                le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
                }
                if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
-                   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
+                   SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS)
                        pi->caps_enable_dfs_bypass = true;
 
                sumo_construct_sclk_voltage_mapping_table(rdev,