{
        const struct mrfld_gpio_pinrange *range;
        const char *pinctrl_dev_name;
+       struct gpio_irq_chip *girq;
        struct mrfld_gpio *priv;
        u32 gpio_base, irq_base;
        void __iomem *base;
 
        raw_spin_lock_init(&priv->lock);
 
+       girq = &priv->chip.irq;
+       girq->chip = &mrfld_irqchip;
+       girq->parent_handler = mrfld_irq_handler;
+       girq->num_parents = 1;
+       girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
+                                    sizeof(*girq->parents),
+                                    GFP_KERNEL);
+       if (!girq->parents)
+               return -ENOMEM;
+       girq->parents[0] = pdev->irq;
+       girq->default_type = IRQ_TYPE_NONE;
+       girq->handler = handle_bad_irq;
+
+       mrfld_irq_init_hw(priv);
+
        pci_set_drvdata(pdev, priv);
        retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
        if (retval) {
                }
        }
 
-       retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
-                                     handle_bad_irq, IRQ_TYPE_NONE);
-       if (retval) {
-               dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
-               return retval;
-       }
-
-       mrfld_irq_init_hw(priv);
-
-       gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
-                                    mrfld_irq_handler);
-
        return 0;
 }