.tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
                          EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
-       .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 
        .apr            = 1,
        .mpr            = 1,
        .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
                          EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
-       .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 
        .apr            = 1,
        .mpr            = 1,
        .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
                          EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
-       .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 
        .irq_flags      = IRQF_SHARED,
        .apr            = 1,
        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
                          EESR_ECI,
-       .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
-                         EESR_TFE,
        .fdr_value      = 0x0000072f,
        .rmcr_value     = 0x00000001,
 
        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
                          EESR_ECI,
-       .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
-                         EESR_TFE,
 
        .apr            = 1,
        .mpr            = 1,
        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
                          EESR_ECI,
-       .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
-                         EESR_TFE,
 
        .apr            = 1,
        .mpr            = 1,
        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
                          EESR_ECI,
-       .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
-                         EESR_TFE,
 
        .apr            = 1,
        .mpr            = 1,
 
        if (!cd->eesr_err_check)
                cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
-
-       if (!cd->tx_error_check)
-               cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
 }
 
 static int sh_eth_check_reset(struct net_device *ndev)
 
 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
                                 EESR_RDE | EESR_RFRMER | EESR_ADE | \
                                 EESR_TFE | EESR_TDE | EESR_ECI)
-#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
-                                EESR_TFE)
 
 /* EESIPR */
 enum DMAC_IM_BIT {
        /* interrupt checking mask */
        unsigned long tx_check;
        unsigned long eesr_err_check;
-       unsigned long tx_error_check;
 
        /* hardware features */
        unsigned long irq_flags;        /* IRQ configuration flags */